I’m going to politely but firmly push back on your absurd and unhelpful assertion.
I’ve seen real-life cases where very expensive boards designed by experienced engineers fail because those engineers overlooked something subtle. A network router where one of the RAMBUS banks was unusable because the characteristic impedance of the tracks wasn’t what they thought it would be. A USB interface that wouldn’t work at speed due to a routing issue. A PPC processor that wouldn’t boot because the designer missed the implications of the processor having an address line labeled “A-1”.
I’m experienced enough to have questioned the “experts” on the 'net. I’m also experienced enough to know the limits of my knowledge and be willing to ask whether there’s something I’m overlooking.
Perhaps some EDA tools won’t connect to pads or flooded zones without routed tracks? I’ve only used Eagle and KiCad, and maybe Altium, OrCad, or some other product requires this? @BobZ raised an interesting question regarding hatched fills that I had not considered, and @baldengineer helped answer that question.
As it turns out, the answers I’ve received here mainly reinforced my original understanding. As to where I asked, KiCad is my primary EDA tool, and this was a question regarding how EDA tools handle filled zones. I feel no shame in having asked my question.
For me it looks that in this thread about 50% answers were written without noticing this first sentence in first post. May be authors can write if they took into account this sentence or not.
My opinion why it is possible that you were seeing the suggestions to connect each gnd via before pouring gnd zone.
Case 1.
When I was using Protel 3 I was carefully connecting with track all GND vias even I used full bottom being GND. The reason: If I missed connecting one such via the process of pouring took noticeably longer time. When I once tried to pour GND layer with 20 GND vias not connected (means they were connected to GND pin at top layer but not connected at bottom with other vias) an hour was not enough to pour bottom GND layer. I didn’t wait longer. After connecting all vias with tracks at bottom pouring took something around one minute (it was working slowly, as pouring was done with series of paralel tracks and Protel was showing it during working (you were seeing each track being added).
Case 2.
I don’t remember exact problems that were generated but when moved to KiCad (V4) it was working even worse than Protel when you left unconnected GND vias. So I had also to connect them all before filling bottom layer GND zone. Problem 100% disappeared with KiCad V5.
Since V5 I see no reason to make connections being internal to zone. Some answers you get were speaking about GND return path but GND zone that (as you said in first post) covers the entire layer will not ensure any better return path if there will be tracks hidden in zone.
If you want (as someone suggested) to consider the thermal relief connection as a hi frequency problem then just count what is the frequency having quarter-wave length of 0.25mm (I use Thermal relief gap = 0.25mm) and assume that up to 1/10 of that frequency you don’t have to worry about your thermal relief connections.
This was a very good question and the only thing I can add is that once you have made a copper pour, especially a partial one, make sure visually that all the GND, or any other net you have assigned to the net are in fact connected.
This seems to be either a bug or a shortcoming in many PCB CAD systems.
One way to visually check this is to highlight the net before the pour, just to get yourself an idea of all the pads that will be connected to the net, then make the pour and check if everything is still selected.
This will confirm the connections. I use thermal relief usually.
The reason I have said ‘partial’ pour is that in some cases you may want a pour, say under a transistor tab for use as a heatsink, and you may then route the rest of the net in a normal tracks and vias fashion. Just beware and be very vigilant in those instances, or you may end with a prototype design full of wire-wrap bits of wire!
And also, as a last recommendation, since the type of boards I design are mostly analogue, audio and instrumentation, the grounding scheme of this type of equipment is critical for low noise , hum, ground loop etc.
So when making a pour, make sure you provide enough distance between the pour and the edge of the mounting holes if you use them.
I mean that let’s say you place some pads here and there to use as mounting holes for the PCB, I have found two ways to deal with mounting holes:
use a free pad that I define as, for ex: 3,5mm with a hole of 3,2mm This hole will be plated, or I use a pad that is a bit larger than the screw head that will be used with a 3,2mm hole(for 3mm screws per ex). A large free pad will actually prevent tracks and pour to be to close to the edge and prevent solder mask. It then become effectively a washer of sort.
or on the edge-cut layer I define a 3,2mm round cut that will probably be cut with a router.
This hole will not be plated usually. Here beware, usually there will be no space on the pour and the solder mask.
The problem with either approach is if the pour gets too close to the pad, when the mounting hardware, say a screw and a washer, are installed, it will actually short the surrounding pour to the chassis, causing all sorts of problems.
I found that mounting holes is a subject that is always brushed aside in CAD discussions, until you find that since they are an after thought, many times, sections of a finished PCB have to be displaced and re routed!
I have made this mistake enough times that now when I start a new design, I place all the connectors, mounting holes and other mechanical considerations firstly, and then I go about the business of laying out the circuit.
It seems obvious but I find very often that all the mechanicals were considered last.
Luc
