Hi,
if necessary I can try to ZIP my whole ( very small ) “test project” and upload it here.
I have let’s say a “connector1” in a sheet “connector1” where pins 1,2,3,4 go to a DB[0…3] bus that then is also a sheet pin of same name.
I have a “connector2” in a sheet “connector2” where pins 1,2 go to a DB[2…3] bus that then is also a sheet pin of same name.
In the “Main sheet” ( that contains “connector1” and “connector2” sheets ) I connect DB[0…3] to DB[2…3]
Now the expect result would be that DB[2…3] of bus DB[0…3] would go … in ‘2’ and ‘3’ … but instead after I export the netlist and import it into the PCB I see that pins 1,2 of connector 2 are NOT connected to DB2, DB3 BUT DB0,DB1 instead.
It’s like "it gets the bus entries in order but does NOT respect/see the numbering as ‘labels’ ".
I do not use buses much myself, but I am fiddling a bit with a test project for diferent variations of buses, and have attached the latest version of it.
At the moment BUZZY2 in the root sheet gets connected to Truck[1] on the left sheet and to BUS_0 on the right sheet.
I am not sure whether it’s a bug or a feature.
Also note the the order of declaration of the members of the Truck bus is reversed (which is legal). If the bus members were connected in the order of declaration, you’d expect BUZZY_2 to be connected to Truck_5.
As a workaround it’s quite easy of course to always start numbering your vector buses from 0, but that is also not ideal.
A test: What does this forum do with two_dots[0…2] and with three_dots[0…3] ?
Answer: It renders them both as three dots.
It has to be two dots for KiCad though.
Hi,
I found a workaround but this behaviour should really be posted somewhere as a bug report.
Fundamentally “if you use busses, use them always in full and label ALL the bus pins even those you don’t use”.
I mean you have this bus D[0…3] bring it around as that in ALL the schematics parts it has to go and then where for example you need only D2,D3 place two extra pins with two extra ( local ) labels D0,D1 and leave them disconnected.
If you don’t do so, it won’t work, that’s the only way I found out to make it generated a correct netlist.
In essence “map all the pins even those you don’t use”, it’s the only way I found out to make it work but this is essentially a bug, it should NOT work like that.
I think you want to implicitly assume that connections should be made simply by numbers matching, but the number is only a part of the complete bus name.
Also note that in my example I included the same hierarchical sheet twice, but that does not mean that bus names (which are local to the sheet) are connected “one to one” to the other instance of that sheet. When going up and down though the hierarchy it splits the buses into separate buses.
Have you looked at the example I posted?
One thing I think you missed and I think is quite important that if you go up a level in the hierarchy, the whole bus can have another name. You have not named the bus in the root hierarchical sheet at all, and that is a part of your problem.
But if you look at the PCB, then neither the “BUS”, nor the “Truck” bus names are used, but instead the bus names defined in the root sheet are used.
Your naive assumption that wires should be connected only because the number in the bus is the same is… well, naive. Take for example some 16 bit computer system which uses 8-bit wide memory IC’s. In KiCad you can draw an hierarchical sheet with only a byte wide databus, and include that sheet twice to expand it to a 16 bit databus.
A couple of comments:
First, always run a DRC before even thinking about the PCB and get the gremlins out first. As an example, you have two bus outputs connected together, which is a no-no.
Second, 6 is a bit different to 5 when it comes to buses. 6 needs bus labels on the bus itself (perhaps to solve this issue?), otherwise it doesn’t work. In your lower bus (in the OP) where you have D[0…3] going to D[2…3], I’d label the bus section accordingly.
See if that works.
