Searching for Symbol (or Other Option) to Simulate an Analog Delay Line

[paru]

Hello,

Can someone recommend a library for Eeschema with ngspice including a delay (line)? I would like to model a time delay in the circuit simulation of several tens of ns. It should be an ideal analog delay independent of any CMOS voltage levels were it starts to operate or RF delay line needing impedance matching.
Alternatively, a tip how to modeling delays in ngspice would help to. I can implement the symbol by myself.

Patrick

[holger]

I do not have a direct answer to your question, but you may post it also in the ngspice user discussion forum https://sourceforge.net/p/ngspice/discussion/133842/ to reach for other ngspice users.

[BlackCoffee]

I prefer LTspice so, most of my experience is based on it. However, occasionally I use pSpice and ngSpice. Normally, I use Berkeley’s documentation but, often I use others, including this link

Here’s a screenshot for useful (Elmore) delay…

[paru]

Thanks a lot for the tip. I also thought about some distributed line model. I think the lumped model will do the job in the first run.

Patrick

[Ste]

Hey, there. Kind of surprised this wasn’t mentioned yet. It sounds like for what you’re trying to do, using the built-in lossless transmission line component seems the most straightforward. Please see Section 6.1 of the ngspice manual.

The idea is to set Z0 of the line and make sure it’s matched at least on the source side with the same Z0 termination. Load side can be either high-z or if you make it Z0 too you’ll need to compensate for the halved voltage when plotting your results. Then, you can set TD to the delay you need to simulate. It’s actually interesting (for me) to use TD directly, because my only experience with using this component is for coax cables where I had to derive an equation to get TD using dielectric constant and physical length. It’s cool to finally see a simple use-case of the lossless tline component where you already have TD on hand. ANYWAY, to use this in KiCad you need a symbol with 4 terminals…so I just used the built-in common-mode choke symbol with a swapped pin order when making the attached test project. It needs some mucking around with the fields for the symbol, but this test project shows the jist of it. Try changing the “Td” value by editing the text directly and run the simulation to see how it changes.

tline_test.zip (2.8 KB)