Schematic line size matching NetClass trace width problem?

Application: KiCad Schematic Editor
kicad introduced a feature that is new to me. schematic trace is now matching net class size. The first time that I saw it was with 6.0.8, Same on 6.0.9.

This is semi-ok except that it creates more work as I now need to add pages and move stuff around to make the larger lines fit.

My current dilemma is with GND. Assigning a higher current (wide kine) netclass to a line leading to GND changes every line to connects to a GND EVERYWHERE! That is no good because then even low current lines are made fat. This is a real problem and not just an appearance issue because it will change trace sizes on the pcb that should NOT be changed,I tried putting a Net-Tie between the fat line and GND but that didn’t work and that stops the netclass from propagating but what a pain! More work and more schematic space, plus it puts an otherwise unneeded piece of copper onto the pcb.

So, QUESTION - anyone see a way around this problem?? Or, am I missing something?

While you can select a line and use Properties to change the line to 0.1524 appearance without changing the netclass, I would really like a global on/off button for the Schematic Editor to toggle display of trace lines between default and netclass - just the display, not actually change the netclass.

For the record my PC is running Linux 5.19.17-2-MANJARO x86_64

FYI: WelshmanJeff previously posted about this. It wasn’t exactly what I am describing but, nonetheless, he received no feedback. [ Schematic line properties depend on net class ]

You have two settings for netclasses - one for the schematic and one for the pcb. Both settings are independent.

  • for schematic: File–>Schematic setup–>project–>netclasses. The value for Wire thickness only changes the schematic dispaly - no influence on pcb.
  • for board-layout: File–>board setup–>design rules–>netclasses. There you can change the value for track-width on the pcb.

On PCB this has been a little ugly for some time. I want Gnd & Vcc to be big traces, but I am unable to connect them to fine pitch pins. It would be useful to have “leader” that was small from the device pin to a wider trace for the “Gnd bus”.

If there is a way to dynamically change trace width for just a segment, I need to find it.

mf_ibfeew Thank you. I will try that tomorrow - too late for me to try now.

Thanks for the advice. It solves 90% of my problem. I set up the schematic with netclass line sizes larger than default, to emphasize the larger traces, but small enough to not crown the schematic. The PCB has the correct netclass sizes for the desired traces. The netclass names propagate between the schematic software and the pcb software but not the sizes, so that works great. Screenshot attached.

Alas, connecting a fat schematic line to GND does propagate the fat line to every other line connected to GND and that is undesirable. Consequentially, if fat lines are used in the schematic then net-ties are still needed. Since net-ties currently create unwanted copper on the PCB I may forgo the fat schematic lines. It is rumored that a new net-tie will be supported that doesn’t create copper. If that happens I will put them to good use. Better yet would be a GND symbol that didn’t propagate netclass to connecting lines.

UPDATE - This is the solution that I’ll be using - Net-Ties. However, before I finalized on this solution I did some testing with unique GND symbols for these different current return paths. In the end it doesn’t really help much because I still need Net-Ties somewhere to bring them to a single GND. Those “no copper” Net-Ties would sure be nice.

I made a couple of special extra GND symbols per this link: