I’m getting feedback from our PCB manufacturer, saying that he found “SameNetSpacing” issues in some filled copper zones of our KiCad project.
Indeed, it looks to me that the filling algorithm violates the “min clearance” setting in some situations. Please have a look to the following clipping of the PCB (captured by “PCB Investigator”):
Case A: the distance between the two vias shown on the left is 1049um, The filling algorithm generates two stubs having a distance of 48um. The clearance setting was 152.4um (6mils)
Case B: the distance between the two vias shown on the right is smaller: 880um. The distance between the two stubs is ok.
The annular ring and drill for all vias is exactly the same.
So if we place two vias in a specific distance, we get this “SameNetSpacing” issues. If the vias are placed closer or further, everything is ok.
Clearance and minimum with of the zone is set to 6mil (0.1524mm), also the global clearance value (default net).
We may control this behavour by increasing the minimum width of the zone, e.g. to 0.3mm. But then we get the same type of problems for a different range of distances between two vias…
What do other KiCad users say about this? Are there any simple workarounds for this? Should I report a bog to the KiCad bug tracker?
{Time to send the slide-rule out for calibration. 12 mils is closer to 0.30 mm.}
I believe you are observing normal behavior of the “Fill” algorithm. It has decided that there isn’t enough space between those two vias to completely encircle both vias. The required center-to-center space is the sum of:
Two drill radii
Two annular ring widths
Twice the Fill Zone’s “Minimum Clearance” value
The Fill Zone’s “Minimum Width” value
(And there’s something rattling around in the empty space in my head, from a few years ago, about how KiCAD accumulates rounding errors unidirectionally for this calculation so the software’s idea of minimum distance between vias is a bit more than the strictly mathematical value.)
If KiCAD can’t meet all the spacing and width constraints at some location in the fill zone, the result is what you see in your screenshot: two lobes, reaching for each other, but not quite connecting. (Sounds like a line from some cheesy romance story.)
Push your numbers through your Texas-Packard cackl-ator, compare them, to the measured via-to-via value in your design, and come back here to report your findings.
Interesting effect, looks like KiCAD dos not check the final finger separation, and that can trigger errors in downstream software that simply scans gerber files.
In this case, issues across this gap are totally ‘don’t care’, but when you are working across language barriers, and with stop/go software checks, that detail can get lost. (ie best avoid this in the first place)
I’d suggest raise it as a bug, and see what is reported back.
It may be that the software can be enhanced to check/adjust that gap, when it has all the info on the pointers…
You are completely right - it was 6mils, not 12mils. I corrected the values in my posting above.
Two drill radii: 2* 152.4um = 304.8um
Two annular ring widths: 2*152.4um = 304.8 (total diameter of annular ring is 609.6um)
Twice the Fill Zone’s “Minimum Clearance” value: 2*152.4um = 304.8
The Fill Zone’s “Minimum Width” value: 152.4um
=> sum is 1066.8um
The distance of the via centers is 1049um, so for me it seems to be reasonable that the vias are not fully enclosed by copper.
It is absolutely ok that the two lobes will not connect when the space is not sufficient. The problem is that the distance between them is below 152.4um. Instead, I would expect that the fill algorithm shortens the lobes not to fall below the min clearance value.
I will upload a kicad_pcb file to this issue which demonstrates the behaviour. You can easily see here that the filling algorithm generates the same net spacing issue. When you move the upper left GND via a bit closer or further to the other GND via and refill layer In2, the distance between the two fingers will be ok. vias_samenetspacing_issue.kicad_pcb (11.7 KB)
Well yes, but the gerbers are what the PCB FAB is looking at.
Of course Kicad displays and generates the info on your PC.
Did you submit it as a bug, with example ?
As far as I know the minimum clearance is related to minimum clearance between different nets, being the same net in this example I doesn’t matter if they are almost touching.
Some manufacturers see it as fishy if the same net violates their clearance. I do however doubt it will create true issues with manufacturing (in this specific case).
We can argue that for (already) connected nets it makes no difference if the copper is connected at that position or not. But finally we request the manufacturer to produce a copper plane with a small gap of saying 48um here. The manufacturer says that he can’t guarantee this and that we should fill the copper or keep the minimum distance.
I would argue that small cap is nicely shorted right next to it. So i am quite certain that you can ignore it if you are not dealing with relevant signals >10GHz. (And maybe even for all frequencies if there is no trace between these two vias on any layer. But here i could be persuaded that a field simulation might be necessary to say for sure.)
I am sure it can. And i am prepared to bet quite a few beers on the fact that this small cap does not matter (what might matter is the interruption of the ground plane if there is a trace above this area)
I won’t bet against you Either if those “lobes” are connected or not, the functionality of the PCB will be exacltly the same for us. So it doesn’t matter if the manufacturer is able to keep the min distance here or not.
On the other hand, I’ve heard from an EMC specialist years ago that he got problems with an unwanted gap in a GND plane, causing electromagnetic radiation in GHz band. But I don’t know if those artifacts are large enough for this.
But finally we are requesting a gap in the PCB, and the manufacturer says he can’t produce it that way. I won’t discuss with him that all of those gaps are ok for us, even if they don’t meet their design rules. So in my point of view, this is an undefined behavour, comparable to an uninitialized variable: In most situations the program will work anyway.
And “SameNetSpacing” is a common check result found by commercial PCB tools, e.g. PCB Invesigator…
This is why i mentioned the fact that the interruption could be a problem.
And it really only can be one if you have a trace bridging this gab (as it can result in a nice slot antenna)
It will definitely act as a high frequency ‘spark gap’ leaking charges.
Apart from our fancy conjecture I’d just place those vias in a way where the zone fill-in algorithm gets a chance to close such gaps. Oh yes, I’d prefer a nice dry red one in lieu of Bier.
Yes, the gap may behave like a slot antenna. My SWAG - based on a few looks inside the enclosures of some equipment operating at 14 GHz, many incarnations ago - is the antenna effects will come into play somewhere between 10’s of GHz, and daylight.
Does anybody want to tackle this problem in SONNET? It might make a good Master’s thesis, or at least a decent article in a trade magazine. And I predict the conclusion will be something like, “For the vast majority of electronic devices designed and manufactured at the present time, gaps like this don’t matter. In the rare instances where they DO matter, the designers are already aware that they matter, and they have effective ways to deal with them.”
Here’s the sticking point: the geometry violates your board vendor’s DFM constraints.
That impresses me as a low-risk, low-effort, technique to eliminate the problem. @Gerrit reports,
. . . so one of the vias needs to get pushed by 18um. (Pulling the Pickett Log Log Duplex out of my pocket protector, that’s 0.7 mils - less than the thickness of cigarette paper.)
Another approach is to reduce the “Minimum width” parameter of the fill zone. Doing that risks creating a sliver of copper that is less than the manufacturer’s minimum width requirement. He will send a squawk to you about the violation, and you’ll respond “Yes, go ahead and fab the boards. We’ll accept the risk that over-etching will open up a gap in the path.”. Which is essentially the same situation you’re already in.
Yet another approach is to explicitly lay a trace through that gap. But you must be careful: a wide trace can violate the required copper-to-copper spacing of the vias, while a narrow trace may violate the minimum trace width. And that is a fundamental problem facing a developer assigned to “fixing” the bug you reported. Should the fill algorithm:
Back off the filled area until the gap (between copper segments in the same net) meets some clearance criteria? This would create a physically larger antenna structure, potentially moving the antenna effects down into an unacceptable frequency range.
Force a copper trace through the gap? Which parameter should be violated to allow the trace: the minimum trace width, or the copper-to-copper clearance?
I am quite content to let the behavior remain as illustrated in the original post. The software has operated according to fully-specified, well-understood, mathematical rules. If the results are unacceptable to me as the designer, then I must apply creativity, ingenuity, and insight to make the results acceptable. Engineers sit at that junction of science and creativity, understanding how the universe operates as it does, then creatively applying that understanding to make a small piece of that universe behave according to their desires. No other mortal creature has that combination of comprehension and control.
Either if those “lobes” are connected or not, the functionality of the PCB will be exacltly the same for us. So it doesn’t matter if the manufacturer is able to keep the min distance here or not.