Review of this intial segment of my Pcbnew effort


This is the last step of creating a board I have been working on for some time. The community has been very supportive and I appreciate that a lot - Thanks!

I don’t want to make any big mistakes when making the pcb and thus I have started by making the top portion of my PCB. I would appreciate reviews, comments and highlights if I am making mistakes - I have never done this before and definitely classify myself as a “noob”.

The piece of my schema I have done looks as follows:


The Pcb designed so far looks as follows:

I appreciate it’s hard to see some of this, so I have zoomed in a bit on the complicated part:

2 questions:

1/Would this work?
2/Any obvious mistakes, lack of best practices?


At first glance there appears to be an issue with the trace that runs next to pin 2 of U1 but I see now that it is the same net. So I would reroute that trace.

Hopefully you intend to have a ground plane on another layer so I would not route the GND net. Connect them to the ground plane with vias.

Also, it may be intentional but it looks like you have the barrel jack backwards. And you should use a wider trace for the power (5V) net.

  1. Probably will work
  2. Don’t use traces for GND. Use a copper zone that covers most/all of the board. There are a few other things but this is your big mistake.


How do you know that the tab (the wide pin, number 4) of your regulator is a ground connection? I looked at a datasheet and pin 4 of the SOT-223 package is undefined electrically. There might be a possibility that pin 4 is actually connected to output which would short the chip. (The TO-252 package uses the tab as output, and many devices of this class use the tab (pin4 on SOT-223) for output. But that isn’t always the rule.)

The safest thing would be for you to leave pin4 of your regulator unconnected unless you have reliable information that explicitly states what pin4 is connected to internally.

I see that you routed a trace past a ground pad (of U2) to connect D1-1 to CP2-2. That is unnecessary. Simply connect D1-1 to the the closest pad on the GND net, or as Seth_h mentions use a copper fill for GND. (Using a copper fill for GND isn’t always necessary as Seth_h alludes to, but it is often a simpler solution.)

I see 1.21GW already mentioned the barrel jack orientation while I was writing the above. Remember, the cable will be plugged into the short end of the barrel jack opposite from pin 1. If you want (or need due to space constraints) the plug to be over part of the circuit, just be careful of tall components getting in the way of connecting power. :wink: Laying out circuit boards is more of an art, but strongly guided by physics.


It should at least be connected to a copper zone for thermal purposes but not connected to anything else.


Instead of drawing some traces and then posting the “result” you should do some research on how to use PCBnew to generate a decent PCB.

Very recently (days, weeks ago) another “beginner” (almost?) finished a PCB design here on this forum.
He started a bit similar to your work, got a lot of advice, which he put into his PCB and he got a pretty decent & profesionally looking PCB in the end.

The design itself was an AVR board with a bunch of MOSfets for some dimmer project.
I think you can learn a lot by reading that whole thread, ad save us from the thime of giving you the same (basic) advise.



Thanks for the feedback so far.

I don’t show U1 here - do you mean the chip on the right hand egde of the image?

I am not sure how to do “vias” and making a ground “layer” – any guides on that? Will that increase manufacturing costs?

The barrel is likely backwards – will fix that!


Agreed! Link the thread please :slight_smile:


I’m searching for it…

Found it:


@SembazuruCDE Ok - so I can safely connect the ground pad of D1 to the ground pad of U2, or if it made it easier, the GND pad on the chip on the right hand edge of my board?

It may seem silly , but is it ok to simply tag any GND connected chip pin to any of my ground points? Also for the 3.3v / 5v line?


@SembazuruCDE, @Seth_h, @1.21Gigawatts, @Gerharddc Updated with all feedback so far:

A little closer:

@paulvdh I will read that thread now ty :slight_smile:


It depends on the manufacturer, but nowadays probably not. I have heard that even today some charge extra for each via hole, but two-layer boards are so standard today that they hardly can compete with those who don’t charge extra.

As for the planes (big continuous copper areas; they are not “layers”) - the easiest thing to manufacture is a plane, because for that they don’t have to do anything :slight_smile:


Except for some rare cases, this is true of any of your nets. You will often find that the traces that you lay down in PCB connect may connect in a different order than how you have it done in the schematic. This is OK and normal. The needs of the PCB is driven by mechanical and with high speed circuits electrical practicalities. The needs of the schematic is only ease of readability and understanding.

I recently discovered a starting with KiCad series that is fairly good. Sean Hymel (of SparkFun) made this series with DigiKey, and it is published on the DigiKey web page. There is a lot of pushing using DigiKey and their libraries. Up to you if that bothers you or not. I don’t agree with the way he down-played and subsequently ignored pin types and ERC in EESchema, but overall it is pretty good. He does describe circuit layers and using vias pretty well (something you have asked about above). Give his series a full watch starting here:
He is also doing this for v4.0.7, so the interface should match. I don’t think I saw him leave the Legacy canvas though… There are some nifty new features in the OpenGL canvas that aren’t available in the Legacy canvas. But the OpenGL canvas doesn’t quite have all the basic features of the Legacy canvas. You may want to get used to switching between the canvases as you work depending of the feature you want to use.


I am watching this series with interest - thank you!

Another ‘How to’ question is how do I achieve this schematic ‘bus’ in the pcb:

I have 5 of these bus io switches which I have connected to a single output (basically this is some form of switch, 5 inputs, only 1 of which will be on at one time)

The rats nest shows a sort of daisy chaining…is there a better way to do this?:

Note the 4 inputs on the bottom and the single output on the right.


Seriously? It is identified as “U1” on the schematic. It should be obvious which trace I am referring to anyway.


NOTE: this would work for with version pre-5 - I’m not sure about version 4.

Whatever the final layout, the FSTD components should be aligned side by side, for example on the same x-coordinate line. Also the 4 connectors, each in the same relative place under the FSTD. Then, after you have drawn tracks between one FSTD/connector pair, you can try to copy or duplicate those tracks and place them over another pair. Believe me, you just don’t want to every one of them manually when they are identical.

For the FSTD to FSTD connections: draw a set of horizontal lines for the bus, above FSTDs. Then draw vertical tracks from one FSTD to those bus tracks. You must use two vias for all but one vertical track, one to go under some horizontal tracks and one to connect it to the wanted horizontal track.

I’ll try to attach an illustrative screenshot later.

In any case, try to first find good fixed locations for FSTDs and connectors. If you have to move them later you will have to redo very, very much.


This is not a perfect example, but should give you an idea. Yours should look more regular: the first vertical trace should go to the first horizontal, without vias. The second vertical goes to a via, under the first horizontal, and then rises back to the front layer through a via which is on the second horizontal track. Etc.


Here is part of the schematic - it’s distinct lines instead of a bus. Maybe I should have learned to use buses, but this is how I did it. Basically you can do it identically with tracks except that you have to use the vias and the second layer because tracks can’t cross each other in the same layer.


This is exactly why I retain my opinion that calling that wide chuck of metal on the part a “tab” is the best practice.


I’d wager a cold beverage that tab in the OP’s design is in fact output, and not gnd.


This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.