I’m not entirely sure about this forum’s policy on design reviews. Somehow my question is related to KiCad and somehow it’s generic. Feel free to tell me if it doesn’t belong here:
I’m designing a boost converter for a PoE application. It translates 20-25V to 48V at a max Iout of 500mA. I have some experience in electronics but very little in PCB design, so I’d like to know if this PCB is in a reasonable condition before I send it to the manufacturer or if there are some improvements i should make beforehand.
To be honest right away, I didn’t conceive the design. It was autogenerated by Texas Instruments’ WeBench Designer, I merely remodeled it in KiCad and assembled the PCB (see here for the original design by TI).
The connections running on the back side are mainly ground connections. Is it better to define a filled zone for ground that encompasses the whole board outline? I know this is a common practice. but are there good reasons for it in my case?
I set the vias right on the actual pads wherever possible. Is this good practice since it simplifies the design and gives a cleaner look, or bad practice because the heat dissipation makes it harder to solder?
dr requests are ‘tolerated’.
I suggest to stick to the suggested layout you can find on almost all the datasheets of the manufacturer, switching power supplies are sometimes tricky.
At a first glance your design is a bit messy, and the thickness of some of the lines doesn’t sound proper to me. Rt1 is unreasonably HUGE!
I suggest you to read some general article on switching power supply, ti has good ones, from what i can see you are a bit far from the target…
…sorry i cannot go further… my eyes hurts.
In general we try to keep forum being about KiCad use. The other questions have higher probability to get better answer at general electronic forums (like EEVblog)
In most cases it is good to have GND filled zone to ensure the best way for all high frequency return currents. High frequency return current don’t go through filled zone back to source the shortest way (like DC currents do it) but they prefer to go just under the current to which they are return currents.
In DCDC converter there are high frequency currents (important is not the basic switching frequency but fast switching currents have lot of harmonics) so generally it is good to have GND zone also in DCDC converter.
But DCDC converters are one of the difficulties designs to make them perfect. I’m not expert in it. I supposed that at link you provided I will se the TI designed PCB to compare with your and point noticed by me differences, but there is no one there.
My take to DCDC converters it to imagine the current way in both switching stages and imagine that they flash alternately. When you look at it you see the changes. The further you move away from the PCB, the less visible the blinking is. The best DCDC PCB design for me would be this when the distance you will not see blinking be the shortest.
Thanks for answering. Unfortunately “you are a bit far from the target” alone isn’t much to go on for a beginner. I’ve read articles and the datasheet and I’m pretty sure the schema plan is sound. After all, TI itself is unlikely to miscalculate it’s own IC so much that it won’t work. Also, I didn’t know how to make the traces any bigger, as the LM’s pins would only allow a size of 0.25 mm
So I looked at the layout example again and it think I realized it now.
For somebody with little design experience, arranging the parts on the pcb is confusing and intimidating at first. You intuitively start ordering them so the rat’s nest looks as “untangled” as possible and then linking them with traces. I simply didn’t think of using filled zones instead of traces, I didn’t even realize the layout example used filled zones, yet they were in front of my very eyes.
So I started fresh, arranging the parts, so that as many pads as possible can be encircled by as little filled zones as possible. That way, it’s possible to maintain a big enough copper area for all high power loops. The two identical SW pads of the LM make sense too now, both can be encircled in a big copper fill, tripling their trace width.
yes, closer now.
The ‘power path’ input connector-> power inductor → diode → out connector is now proper, this was the easy part.
Now you have to identify the path where fast switching currents are flowing and minimize the size of the loop (inductance).
Probably could be beneficial to physically divide the part of gnd that carries fast currents from the part that is used as ‘reference’ by compensation and fb parts.
EP seems to be disconnected from gnd. this could be right, but i suspect not. double check with the datasheet.
Your gnd plane seems to me cut too much by signal traces.
You have to try to protect the feedback to the regulator from possible switching noise as much as you can.
LT has a term which I like to use; it is called “hot loop”. That is the current loop in which high dI/dt currents flow. Getting minimum stray inductance in that loop is your top priority.
In your boost converter, that is from the SW pins out through D1, to the output capacitors (mainly Coutx1 as it provides the lower inductance path) and back to the power ground pins of the IC.
Having a ground plane as the next layer under the topside components will help significantly.
My observation is that your lower layout is not too bad wrt layout of the hot loop. But I do not like Cout1 and Cout2 in series. Why are you doing that? How do you know that they will share the voltage? Can you use a single capacitor there?
Input capacitor, Diode and power switch, output capacitor.
Rationale:
It’s the Capacitors that take care of the high frequency content of the switching noise. The connectors are just for bulk power delivery. Wiring can (and will) act as antenna’s, (both send and receive), but it is still the capacitors that filter out the noise. Rotating Cin1 180 degrees and putting it just under the inductor puts it’s GND (with high AC current) close to the IC and reduces the area of the “hot loop”.
The inductor also is not terribly important. Because it has inductance (duh) it already resists fast changes in current. It is both the diode and the power switch where the action of fast changing current paths occur, and that is where noise is generated. Minimizing changes in the current path is a good optimization, and SMPS IC’s with built in diode (or synchronous active switch) are best. Your diode is close to the IC with power switch and this looks quite good. The node in between the switch, diode and inductor also has rapid voltage changes, and these get capacitively coupled into the GND plane, and into a track that appears to be the voltage sense feedback. That is not so good. A bit of resistance here is not important (the inductor already has much more resistance then the tracks) so making this track not wider as needed is better (although it’s already relatively wide because of the pads).
For more of this, search for “hot loop” in combination with “SMPS”
I tried to have a look at the datasheet of the LM1. At first it does not find electronic stuff at all, and when trying to narrow it down I find stuff like volume control thingies from Bosch. Why is Rt1 so ginormous?
Cout1 and Cout2 in series? Why?
I don’t like the 3 tracks cutting though the GND plane. They destroy the integrity of the GND plane right at the point where it is most important. I have not fully anazyed the schematic, (no datasheet, not enough motivation) but in general, there should be no slots in the GND plane, and definitely not in critical area’s. There are some exceptions, for example you could make a small hole in the GND plane below the node of the Switch / Diode / inductor to reduce capacitive coupling here.
Gosh. I posted this before I read Bobz’s post, content is pretty similar so we probably have some points here
If I’m not misreading TI’s recommendations, this is what they recommend. In the plan under Coutx, it says “Qty=2”. Is my interpretation even correct, or does this have a different meaning?
The IC’s datasheet indeed states that it should be connected to the PGND plane, but I missed this since the schema generated by WeBench shows it as floating. That’s problably because this GND connection is purely for thermal relief and serves no electrical purpose. Definitely a pitfall if you rely on the example too much.
I was wondering too. Turns out, it’s actually a 0402 size and I accidentally swapped the first two numbers… Thanks for persistently pointing that out.
Thanks for your input so far. According to recommendations:
Rt has been swapped for the correct footprint
Traces on the backplane have been removed wherever possible.
The GND backplane behind D1 and L1 has been interrupted to reduce capacitive coupling.
I’ve been watching this thread and I think you need to take a hard look at how Cout1 & Cout2 are wired.
Could you explain why you have them wired in series? Two 10μ in series will have a capacitance of 5μF - why not simply replace them with a single 4.7μF? That’s a cheaper approach and will take up less space on your board.
If you’re looking to get 20μF, then you need to wire them in parallel.
i think it’s supposed to be 2 in parallel for lower parassitics…
I don’t like the vout fb under the inductor, but i see no easy cleanest route.
I have seen somewhere else the openings in gnd under the inductor and kinda understand the reasoning behind, but does not convince me 100%; never done that. The openings under the diode instead i definitely don’t like (usually is part of the fast switching path, so better to avoid EMI).
Indeed. For the part in between the diode and the power switch (inside the IC) is where you have the fastest current changes, and putting the GND plane below it to improve the GND return current path is definitely more important then lowering capacitive coupling. If you make a cutout in the GND zone here at all (I’m not sure it’s an improvement) then it should only be under the track that goes to the inductor.
Routing the voltage feedback under the inductor is also not good.
YES!! Unless voltages are very high (>400 - 500?) parallel capacitors make a lot more sense. Switcher outputs often use multiple capacitors connected in parallel.
Thanks for clearing that up, I’ll fix it. I’ve never seen this though. Is it common to abbreviate components like this, or just a lazy engineer?
Yes, this is problematic indeed. I could make the traces on the back side, making a large cut in the GND Plane. (What is the problem with this by the way? Parasitic capacitance on the Vout line, or ground loops because of different resistances around the cutout…?)
I could also go all the way around Vin1 on the front side, leading a short part of the connection between positive input and pins 3 and 6 of the IC on the backplane. According to the LM5851’s datasheet on page 4, this connection is for power delivery and, I assume, should be less vulnerable to interferences. Is that about right?
That final layout looks deceivingly simple. It’s almost as if it took no effort at all to create it.
Some last remarks:
Why 6 via’s in the VOut net towards the connector. That can be routed on the top layer (or both top and bottom) You already did a similar thing on the input. With only 500mA of RMS current, you don’t need very wide tracks, and routing both of these on only the top layer would have been plenty.
I think I mentioned it before, but doubling Cin1 may be useful. Then the extra capacitor can be rotated 180 degrees and put in between the inductor and the SMT parts (Css1 and Rfbb1) This extra capacitor reduces the size of the “hot loop” on the input side, while the capacitor on the right side helps filter EMI entering or leaving the PCB.
Be careful with the mounting. A metal washer may short the output to GND. Using plastic washers or standoffs will prevent this.
I didn’t followed the discussion and I’m not trying to go into project details.
Just only short look at last PCB pictures.
Knowing myself I can say that I would use a little bigger Rt1 to route that one track that breaks GND under Rt1. I’m not saying that I know that it is important. I just simply would do it that way as I hate to break continuous GND.
Even as a beginner, I can agree. The importance of unblocked ground return paths seems to be the favourite topic of any author on the internet.
But aside from the good practice aspect, could this break in the ground plane cause any actual problems in my case? It doesn’t stand between any connections to the ground plane and the ground terminal on Vin, does it.
I’m not sure I understand. The connectors for Vin and Vout are throughhole components, at some point I have to change to the bottom side.
That is indeed the pin 1 marker for the IC, I completely overlooked it there.
