Through hole (plated) components, by default, have a pad on every layer so they are already connected to the bottom side.
You should not expect problems but it is not true that this break is not between any connections.
During second phase of DCDC working the current is flowing from Cin1 through L1, D1 Cout1&2 back to Cin1 GND. Current is not flowing in thin strait line but is spread around the copper. So imagine an ellipse containing these via pairs near Cou1&2 and the input GND. This ellipse is partially beak by this one connection at bottom.
Looking at it I see a problem for this current as it can not find shortest way to Cin1 GND pin and need to go through these 6 vias near Vin1 GND connector. If you had via near Cin1 GND pin the way would be shorter = less impedace.
You may be surprised but current you should be looking at is not flowing from Vin GND terminal but from Cin1 GND terminal. External connections have enough high impedance so that high frequency currents flow not from them but from local capacitor.
Not exactly. At inner layers it is not connected it can have or can not have pads.
See: