Replicate layout doesn't works with bus in hierarchical schematic

[warcomeb]

Hi,
I am trying to use replicate layout plugin in a project where the main sheet contains a subsheet that was replicated (for 4), this subsheet go out with a bus. Every bus is connected to a connector.
But when we generating the netlist, only the bus of the original subsheet was connected, and the others no. We can’t understand why!

Can you help?

Thanks
Marco

[MitjaN]

From the description I assume that connectors are located in the main sheet. If that is the case, the plugin will not replicate connections to footprints which are not contained within the sheet that is being replicated.

[warcomeb]

Hi @MitjaN ,
thanks for your replay. The situation is the following:

The second bus line is not connected when generate netlist. The connector is on the sheet “ANALOG_INPUT”

[MitjaN]

If I understand correctly you don’t have the ratsnets lines between connector in ANALOG_INPUT and circuit in CONDITIONING_20V_15V.2. If that is the case you have connectivity issues and this is a KiCad issue.

[warcomeb]

Thanks! Yes, you are right, we don’t have the ratsnets lines between connector in ANALOG_INPUT and circuit in CONDITIONING_20V_15V.2.

Ok, anyone had the same problem with this KiCad? Is it our net name wrong?

[warcomeb]

Anyone can help us? We can’t figure out how to solve the issue!

[paulvdh]

I think you have to name both the individual wires and the bus itself in the hierarchical sheet.

Have a look at this:

Resulting in:

Note that only members 0 through 4 are part of the named bus, and those are the only connections that get though the hierarchy.

Note that the names are case sensitive.

Note that “BUS_0” also gets through the hierarchy, even though it only has a local label and does not appear to be physically connected to the bus.

Note that pins 5, 6, and 7 of the connector do not get connected, even though they appear to be connected to the bus, but the bus names do not match.

On the main schematic, it’s just twice the same hierarchical sheet:

Note the color differences between the wire and the bus. I do not know why the left “Some_Bus” label is in blue, while the right one has the same colors as a wire. If I delete the one on the right sheet and import it again, it also becomes blue.
Edit: This appears to have to do something with the bus name. If I go into the hierarchical sheet and move the “BUS_[0…4]” name, then the color of the hierarchical name changes, but there appears to be a (minor) bug here (only in the color).

Also note that on the hierarchical sheet, the name of the hierarchical pin is used, and not the name of the bus.

Here is the project, so you can look what’s inside and experiment with it.
Edit: I tinkered a bit with this example project and added different options to implement buses. It is now also free of ERC violations.
2022-07-06_asdf_hierarchical.zip (13.6 KB)