Protip: nicer via stitching


“Hidden text” option was selected here. Did not know about that option, thanks.


I have created a via on a 4 layer board as described here, if I have GND net on the copper pours of 4 all layers. When I create a via with a netname GND, does it connect to all the ground on the 4 layers, visually I am unable to see the color of the via changing when I disable a particular layer, it stays in a cyan color at the holes. Is there a way to get visual confirmation that the via is stitching all 4 layers

Corresponding area in Gerber


Is there any way that “tenting” can be controlled for these simulated stitching vias? When doing thermal vias you want to inhibit solder mask so you can solder to the “vias”, but in electrical-only cases you typically would want them “tented” so that you can put silkscreen over them. I always get a hole in my solder mask even when the mask layer is enabled in the Pad properties.


Did you check the gerber file for the solder mask for the vias you want tented?
What does it look like?

If there is soldermask defined over the hole it’s up to you and your fab house to work out a scheme to get those soldermasked vias made tented…


Yes, I checked the Gerber file; that’s how I know that there is no solder mask over the vias. I am unable to get solder mask (tenting) to cover these vias. All of the small dots in the solder mask layer shown below are vias that I would like to be covered with mask.


If you - as per the thread - use pads as vias (placed as footprints) you can set the pads to not have soldermask holes where they are - just deselect the circled options.


I used this tricks to create a bunch of stitching vias and they worked. However, i run into an issue when I am trying to use the FreeRoute tool to do auto-routing. it complains about duplicate component with REF** that apparently coming from this stitching vias. Can anyone help?


Never trust the autorouter.

OK, now that I got that out of the way.

Have you tried giving each one a unique identifier? You should be able to assign it manually for each via.

You could also created a schematic component and have those tied to the same footprint you’re using for the via. Again, more hassle, but that would put each via into the flow of being annotated.


The new feature of the nighties is support for a kind of via made for stitching. They doesnt seem to have a reference so I wonder if that would help here


Is this feature implemented? If so where is it?

On 4.0.7 and it’s not working automagically.

Via stitching and Design Rules

Kicad version 4 does not get new features. New features are only added to development releases (so called nightlies). This will be released as kicad 5 in a few months.


OK I have it working, first you must draw a track from the reference net (AC2) and the track must remain if you switch away from OpenGL otherwise you end up with my previous picture.


I tried this and still get clearances around the via pads. Any suggestions?


Has anyone come up with a better method for saving vias from being annihilated by re-importing the netlist with “delete extra footprints” enabled? The problem is that I, like many of you, I’m sure, add vias to fill in ground pours, to stitch grounds together, etc., which are all done on-the-fly. It seems very tedious to go through and figure out how many vias I’m going to need, then add them to my schematic, associate them, generate a netlist, and then re-import. And then, oops, I need 2 more, so I have to go do the whole process again. It’s a bit brutal. This problem is so vexing that I’m thinking about figuring out some kind of Python script workaround.

Anyway, if anyone has any other ideas I would love to hear them.


In context of mounting holes @1.21Gigawatts mentions locking them.


Holy crap. That worked. I had it set to “Lock Pads” before and it was killing them. I changed it to “Lock Footprint” and now they’re persisting through the re-import. Brilliant. And so simple it’s crazy.

Edit: Oh, and duh: Thanks to you and @1.21Gigawatts!


I followed the guide (KiCad 4.0.7) and have one odd situation. I have a 2 layer design with ground planes on both sides, which results in some dead zones on one side or the other. I put in one of these stitching vias, expecting that a redraw would now fill the zone, but it’s not doing so. Quite the opposite - it’s clearing the copper around it!

Is there a way to make the via “connect” to both planes without drawing a trace to/from it?


Did you set the correct net for the pad?


Nope! That was the problem. I assumed it’d have figured it out, but obviously not.

One annoyance was that I couldn’t set the net in the footprint editor - it was grayed out. But once placed in Pcbnew, I could edit the properties, set net to GND, and all was good.

I guess it makes sense - might want to use it to stitch other types of planes.


26 posts were split to a new topic: Vias and a project discussion