Shhhhhhh! That video’s still unofficial! 
Uh…it’s listed on your user page…might want to unlist that
I’m fine with it being seen, I just don’t want to blow the trumpets!
So I just tried a variant on this that is similar to what I’m already doing for mounting holes. This solves the permanence problem if you change other footprints and allow deletion of old footprints on netlist import. Not as fast as the pure pcbnew option, but even more stable.
I generated an array of pads connected to the appropriate net in eeschema. I set them to my stitch via footprint and imported them into pcbnew and placed them like any other component. A little tedious to place the array of pads, but once it’s done, it’s done.
I like that idea. It would be confusing if all of the via stitching disappeared after a secondary import.
And I normally do a lot of secondary imports in the course of a layout. Schematic and footprint tweaks, and so on.
FWIW I already put mechanical features like mounting holes on the schematic and in cvpcb so they (re)import correctly and get connected to nets like GND. If they start cluttering the schematic page I shove them on to a second page.
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I didn’t see that anyone had mentioned this:
One problem noted with this method of via stitching is that the stitches get removed if you re-import the netlist. I found the way to fix this is to select the stitch vias and lock their footprints. Then they can’t be removed by accident.
This has been brought up a few times. That works, or just don’t select Delete Extra Footprints. I didn’t realize anybody actually used that… I just remove footprints manually.
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The method I describe does not lose stitch vias on import, but has the somewhat cumbersome need to add the vias as a component to the schematic. This is not a very big probelm as I make one and copy/paste blocks until I have more than enough. I delete the excess vias as part of final clean up.
@c4757p @ChrisGammell Kindly upload videos on Vimeo as well. It is hard to get Youtube running on my computer. Viemo is free too. 
Hey guys,
Just tried out this trick and it works well, but I have an issue with annular rings on all the layers. If I want to connect something from layer 2 and 3 on a 4 layer board, it creates an annular ring on the top and bottom layers for now good reason.
Is there a way to to turn this off? Poked around, but didn’t see anything.
I see your stitching vias don’t show the reference value when placed in pcbnew. I’ve set reference to invisible both in footprint editor and confirmed it’s invisible in pcbnew. But it won’t go away?
Same problem here, using stable 4.0.0.
They don’t appear until i restart pcbnew.
You saying you want them to appear when invisible? I want them to disappear.
Edit: I had the “Hidden text” option chosen under “Render” tab.
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“Hidden text” option was selected here. Did not know about that option, thanks.
I have created a via on a 4 layer board as described here, if I have GND net on the copper pours of 4 all layers. When I create a via with a netname GND, does it connect to all the ground on the 4 layers, visually I am unable to see the color of the via changing when I disable a particular layer, it stays in a cyan color at the holes. Is there a way to get visual confirmation that the via is stitching all 4 layers
Corresponding area in Gerber
Is there any way that “tenting” can be controlled for these simulated stitching vias? When doing thermal vias you want to inhibit solder mask so you can solder to the “vias”, but in electrical-only cases you typically would want them “tented” so that you can put silkscreen over them. I always get a hole in my solder mask even when the mask layer is enabled in the Pad properties.
Did you check the gerber file for the solder mask for the vias you want tented?
What does it look like?
If there is soldermask defined over the hole it’s up to you and your fab house to work out a scheme to get those soldermasked vias made tented…
Yes, I checked the Gerber file; that’s how I know that there is no solder mask over the vias. I am unable to get solder mask (tenting) to cover these vias. All of the small dots in the solder mask layer shown below are vias that I would like to be covered with mask.
