I have problems with this hierarchical sheet:
I wonder if the problem is because KiCad can only support one label name per net, but you have low0 through low7 shorted together to CS. Only one of those 9 net names will win and be used as the net’s name.
Also, all your high0 (and high1, high2, high3, etc) local labels will be connected even though they are “sourced” from different busses. What looks like two different busses will actually be handled as a single bus because the local label names are the same.
Also, please provide your KiCad version number. Busses are getting an overhaul in v5.99 (read as early v6 pre-release) so I would expect the behavior in 5.99 to be different than 5.1.9 and earlier.
I had a peek at your project It’s a quite involved project, and today I’m not in the mood to spend enough time on it to get to know which is which.
My first guess is that you also have to put a label low[0…7] on the bus itself.
Thanks! This solved problem 1 and 2. Now I need just to connect the two buses pin[0…15]*8 and port[0…127] somehow.
I’m using KiCad 5.1.9.
KiCad’s support for busses has been neglected for quite a long time, and there is not much functionality in a bus.
It is legal (and also common) to have multiple labels on the same net, and KiCad V5.1.9 just merges the nets together silently and picks a name.
I don’t think that the *8 part is supported.
Simplest way for your last fix is to just draw a lot of horizontal wires and then place pinNN on the left side and portNN on the right side of the same wires.
It may seem like a lot of work (250 of those texts) but in KiCad it is mostly holding the [Ins] key for a bit to use the auto repeat and increment for placing both wires and labels.
Such things are best tested in a small project.
KiCad-Nightly V5.99 has gotten a lot more support for buses, but I’d have to go read the manual myself for what sort of things are going to be supporte in the next KiCad version.
Thanks, you are right, I just forgot port[0…127] on the top level schematic, now it works as well with multiple labels on one net in the hierarchical sheet.
So all of your problems are solved now?
You must be a happy man 
Also:
I believe you have to use two dots for the range, and not three. You seem to have used two dots in the schematic, but three here on the forum.
(Just saw I made the same mistake in post Nr3.)
EEschema manual also uses two dots in section:
There was some problem that an imported hierarchical bus pin like pin[0…15] can’t be connected to a bus named pin[16…31], but I could solve this be using some temporary names a[0…15], b[0…15] etc.:
Since you have several sheets that appear to point to the same schematic, check out the Replicate Layout plugin here. With it you should be able to lay out one of the level-shifter.sch subcircuits and then let the plugin replicate that layout for all the other instances of the level-shifter.sch subcircuits. Similar idea for the other schematic files.
Yes, this is a nice plugin. I’ve used it for another project:
https://www.eevblog.com/forum/projects/4-channel-adc-10-mhz-8-bit-design/msg2016445/#msg2016445
There is a schematic sheet with these components:
(And only these three components)
For a sub schematic that is used so many times the Replicate-layout script is indeed something you want to use. But these three components are probably difficult to fit in a compact space with that script. However, if you put two of these filters on the schematic, then you have an even number of components, which can be fit relatively good in a rectangle and makes use of the replicate-layout easier.
Placing one footprint, and then using the replicate layout script for the other two is also not very effective. You still have to place 128 “reference footprints”.
I think you are over-using hierarchical sheets here. I think you’re better of when you draw (copy & paste) 16 of these filters on the same sheet as the MCP23S17_SO and then use the replicate-layout script to replicate that whole sheet 8 times.
The CS pin is connected in series to pin 47 of sheet i0-module and connected in parallel to low[0…7], so all the signals are shorted. Hence, it is not possible to connect CS pin to “Sheet: CS”.
High0 of sheet CS is connected to high0 of sheet MOSI, because of the same label given to the different signals. Try changing the label to avoid shorting.
To connect the pins from “sheet CS”, high[0…7] to the individual CS pins of “sheet: io 16-0…7”, label the bus as high[0…7].
To connect, pin[0…15] of “Sheet: io16-0” to port[0…15], label the bus as pin[0…15].
