Preventing Insufficient Inner Clearance Issues?

Layout
1

I’m laying out a new PCB in KiCad and I plan on using Advanced Circuits to produce the boards because I need 2oz copper on the outer layers on a 4 layer board. The inner layers will carry IC signals.

Advanced Circuits says their minimum inner clearance tolerances are .010" .

I want to setup KiCad to prevent me from violating this inner layer minimum clearance.

Can somebody please tell me where I should enter this info in KiCad’s global design rules. I already have the outer layer minimum settings programmed correctly.

Below is what Advanced Circuits has to say about Inner Clearances. I’m just afraid of getting this wrong.

  1. Insufficient Inner Clearances
    Inner clearance is the minimum distance from the edge of a hole to any adjacent, unconnected, inner layer copper. Sufficient inner clearances help ensure that your drill does not cause shorts to your inner copper layers. This is important for both plated and non-plated holes, as non-plated holes may either cut into an adjacent trace or cause shorts during assembly.

Requirements: A minimum of .010" inner clearance is required and .015" is preferred.

Resolution: Most inner clearance issues can be resolved if negative image inners are provided, but it is preferred to not modify these. Setting these clearances in your layout software is the preferred method, as this will maintain intended connectivity. While most layout packages provide this as a DFM check, not all do. Those that do not can usually be manipulated to check for this violation by setting spacing and annular ring higher.

General guidelines: Spacing + Annular ring = Inner clearance. Another trick that can help resolve problem areas is to move the affected traces to outer copper layers, where this is not an issue.

2

I understand that this can only be the problem if your net’s clearances were smaller than 0.01". If the net’s clearances are bigger than 0.01, this will take care of itself with no intervention required from your part?

3

Yep your right.

Thanks for answering the question.

4

I’m seeing the same issue with Advanced Circuits and a Kicad design. If I increase Design Rules->Net Classes Editor->Default Clearance to 0.01" I end up with a ton of DRC violations due to pad->pad spacing, pad->trace spacing etc that don’t appear valid (these are on parts with a less than 0.01" pin spacing for example).

Is there some way to adjust just the inner clearance or is the idea to change this to 0.01" and ignore the DRC violations that pop up?

5

I’m interested to know if KiPadCheck could help you?

6

When Advanced Circuits says “Inner Clearance”, they are referring to Drill->Feature (http://www.4pcb.com/media/freedfm-tips-tools.pdf).

In Kicad, you can use the “Via Dia” to set the via drill offset to other features. Then, if you have through-hole parts, you adjust the footprint’s pad’s “Net pad clearance” (under Local Clearance and Settings) to 0.01".

7

This question, Advanced Circuits Insufficient Inner Clearance, was exactly the issue I was having. During layer selection in their online FreeDFM tool I was selecting ‘positive’ polarity for 3v3, and negative for gnd, entirely misunderstanding what they were asking. When I switched to using ‘positive’ polarity for both layers Advanced Circuits DFM had only a few questionable things that were spotted.