Advanced Circuits Insufficient Inner Clearance

Trying to run DFM on my design at Advanced Circuits and keep getting back Insufficient Inner Clearance on all the vias. The require clearances of 10mil which I use for my ground pours and routing. Judging by the picture they don’t process the gerbers on the inner layers correctly and think the the annular ring is the clearance. They say as much on their website: “We can resolve most inner clearance issues if negative image inners are provided, but we prefer to not modify these” Now is there a way to create a negative inner gerber with KiCad?

Here is a link to the picture of the problem area.

Nevermind, I just realized what it was. When you submit files to Advanced Circuits there is a choice you can make for your inner layers - polarity: negative or positive. I thought they were trying to see if the inner layer was ground or power plane, which was weird. So I selected negative. Turns out the polarity means that the Gerber image is negative.

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Nelsa, I don’t know the official rules on such matters but I am not offended if a Forum member occasionally mentions that a particular business performed exceptionally well, or exceptionally poorly, in some area related to PCB design. The key words in that sentence are “occasionally” and “exceptional”.

The original problem that caused @ArtG to start this thread has already been solved . . . 9 months ago! The topic of trace width is unrelated to the problem. You have placed similar posts in other topics. It appears that you are trolling through old topics, looking for an excuse to advertise a particular business. In my mind, this case doesn’t even provide an excuse for placing an ad, so you have settled for half an excuse. Please don’t compromise the usefulness, or the integrity, of this Forum with ads like that.


Negative layers is legacy.

Beacuse they get smaller in size it was useful in the Era of 1200 baud modems.

They could safely be removed from today’s tools.
Just creates problems.


Negative-imaged layers are still quite useful.

The default representation of soldermask layers - in both the native CAE applications I’m familiar with, as well as the Gerber files generated by those programs - is a negative image. (The defined areas in the rendering show where soldermask will NOT be placed, rather than where it IS placed.) This is an industry practice so deeply embedded, and so intuitively understood, that it is almost never mentioned. I don’t think it’s done to decrease file size, but rather because it’s a psychologically effective way to convey the concept how to construct the layer, and what its purpose is.

Sometimes when a layer with a large proportion of filled area is printed (i.e., on a laserprinter) it is easier to comprehend the structure and routing of the layer if it is printed as a negative image.



I only thought about power / ground planes.
There negative layers are error prone.
ODB++ support for kicad?

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