The lack of capacitor will not disturb proper operation but can lead to not pass EMC testing.
In CM sense you can understand SMPS module as AC generator (all harmonics of working frequency) in serie with its internal capacitance connected between GND and isolated GND. During EMC measurements you can assume that it is loaded with 150 ohm resistor and few mV at that resistor is too high (that 150 ohm between isolated GND and GND). The higher frequency the lower harmonic amplitude but C+R forms the high-pass filter so you get almost the same amplitude of each harmonic.
When you add capacitor across isolation you form capacitor divider with that internal capacitance so dividing the CM AC signals respectively. When you add ferrite beads in serie with input or output (each time both lines) you can form also an LC filter to limit the disturbance from SMPS at isolated GND.
According to:
to fulfill the class B (not industry, but home usage) EMC requirements you should block the isolation with two 330pF/1kV capacitors (table at bottom of page 3).
As I prefer to use not only enough solution but better then enough when I used recently such DCDC to power isolated RS485 I used also ferrite beads in supply and CM choke at RS485 output.
This is for an Atlas Scientific pH Probe and the controller for it requires electrical isolation from the rest of the circuit in order to give reliable readings.
Priotr’s response for the 330pF capacitors is much better than mine.
But it does remind me of something else:
The small / cheap / chinese isolated SMPS blocks tend to need a buffer capacitor on their output for a stable output voltage. Check this with your particular SMPS module.
ADM serie isolating not only signals but also outputting power generates so high disturbances at high frequency that I have never decided to use it. According to app-notes you should form a capacitor by overlapping GND zones (at internal layers) and you hardly get a disturbance level below EMC limits.
The signal isolation in ADM also generates at high frequency. I used it in my project in 2004 and got a hill in EMC measurements at about 400MHz but fortunately under limits. I had no isolation blocking capacitor those time as my strategy was to have DCDC with small capacitance (4pF) and 4kV isolation with anything else protecting it (no Waristor).
I know nothing about ISO1540+EMC.
Likewise a high-impedance resistor can be added between GNDA and GNDD to stop the CM voltage “walking” to dangerous levels (but this would be strapping via 10MR GNDA to chassis and GNDD to chassis)
I personally would never leave the secondary side 100% floating either for safety, emi or general best practices … but some do
This is true only if the distance between the trace and its image plane is very small, which will not be the case in a normal two-layer board. In order to minimize loop area by means of image planes, you need at least four layers. In most four-layer stackups, the distance between L1-L2 and between L3-L4 is very small, so mutual inductance is high. You will not get useful mutual inductance i.e. effective image planes between the top and bottom layers of a 1.6mm 2-layer PCB.
This sounds like complete nonsense to me. When layers get closer, capacative coupling gets bigger, but not inductance. The return path will be the path of least impedance, and at higher frequencies the loop inductance will be the dominating factor. And loop inductance increases with the area between a track and it’s return path. Smaller loop area is less inductance. With a 4 layer PCB the GND plane sure is closer to the tracks than with a 2 layer PCB, but the principle stays the same.
We’re probably discussing two different physical phenomena here, and both will influence return current path.
One is Loop area, where the impedance is related to generating magnetic field. The bigger loop area, the harder for the RF current is to flow. Its effect is clearly measurable even with typical 1.6mm dual-layer PCBs.
Mutual inductance (the cancellation effect of two conductors with opposite current directions) is another factor.
They are both related. if a trace and the return plane are tightly coupled and thus high mutual inductance, the magnetic field will reduce due to the counter current flow, this will reduce the inductance
But the assumption that we need tight magnetic coupling (small PCB thickness) to cancel the effect of loop area is not right in typical (non-extreme) layouts.
how much you need and how much can be tolerated are other considerations when a card is being designed. You might consider clocking at 20MHz is slow enough that it shouldn’t be a driver on a controlled stackup and so be it. That however doesn’t change the fact the proximity of a plane has a role to play and as @JuliaTruchsess was pointing out, if you want to take credit for the return current flowing below the trace then this does need to be considered
My point is, even without tight coupling it’s crucial to keep the loop area small. And you’ll have huge EMI difference if you separate the return trace by 5 then 10mm, and none of these will be “tightly coupled”.
I’ve designed pcbs for about 15 years and while you can learn much from reading, there’s nothing like having a real ‘first design’ being pulled aside (in a friendly way!) by your peers!
One thing that wasn’t mentioned until the end, nearly: I thought one of the advantages of internal planes (one gnd, one power) was to provide better decoupling of the power rails.
Any case, off to read up on emc compliant pcb designing.
I also learned a ton from this. I decided I wasn’t happy with a few things and opted to shrink the board and remove the isolated zone that was in the bottom right. I can buy a dedicated board for that which will be cheaper than having the parts on this board. Plus it gives a bit more flexibility in that I’m not locked into that particular pH board.
Anyway, that and I removed the sht31 temp/humitidy sensor and went with a DS20B18 instead as the DS20B18 is cheaper and 3 times the size making reflow soldering a bit easier.
Anyway, I’m thinking I’m almost ready for production. I was going to have JCLPCB do the assembly, but I think I’ll do it myself as there aren’t too many parts and I already have quite a bit of the parts on hand.
I’d clean the design up a bit further to reduce number of track vias and ground plane slots.
And please remove the VIAs on the pads of your regulators, you need to escape a pad before. Otherwise you risk your solder paste will be sucked away and you get bad joints this way (this was explained before in this topic).
One more note, I’d avoid putting stitching vias which are not within your copper fill. So even if your clearances are met, move the vias away from P12v net near your U5.
I am surprised how many VIAs INDYMX used there (but I have never done a circuit where lot of power have to be dissipated). I suppose that as there are so many of them then they have probably small diameter. I have read that if the hole is smaller then 0.3mm then it does not steal solder paste, but I have no experience with it.
And also have in mind that he have written:
I’m not sure if that means that you plan to handsolder it or you have your own reflow oven. It could be hard to do if you don’t have something more than just a soldering iron.
I have heard (never seen it) that amateurs if need to solder the IC with thermal pad they do one relatively big hole under it and solder it from bootom side filling the entire hole with tin.
