I did this, I didn’t find anything weird, just the tracks that I laid down.
Sorry about the confusion about the “weird loops”.
When PCB’s get more complex and a net has multiple connections, then sometimes you make detours in the tracks to connect them to other pins in the same net, and then later, when you do a review you see that a long detour can easily be avoided by re-routing some tracks.
I did not mean to imply that KiCad would add “weird loops”, just that you sometimes do this yourself when laying tracks on a PCB when you loose overview. It is sort of parallel to the placement of U13 in your first iteration. The IC was on the right, and almost all tracks went to the middle or to the left.
This is a relatively simple PCB and I would not expect many of such things in this board, but highlighting most nets to get an overview of the complete routing of those nets is a standard procedure in reviewing a PCB before going to final production.
Ok… Makes sense. Yeah, I did review it and didn’t see anything that stood out to me as odd like that. I did find a few that I could optimize a little though.
Wow. Night and day difference.
Just goes to show how moving a few components about and thinking about the routing can make a difference.
I think because 4 layer boards are comparatively cheap and readily available it makes some people lazy with their layouts. In the past I have made trainees layout boards on 2 layers even if I know that the product would support a 4 layer layout. Makes em think!!
Anyway, good job well done 
2 Likes
Some time ago I read a story about a PCB designer that tries to find complex multi layer designs and then contacts the company who makes the designs and then makes them an offer to redesign the boards.
Apparently he has made some offers to re-design a 12 layer PCB into an 8 layer PCB and do the re-design for somewhere around EUD6000. Firs reaction of companies is often “cannot be done” or: “The board already works, why spend USD6000 on a re-design?”, but later those companies contact him to redo the PCB, because in the long run the lower number count saves on production costs and is worth it.
He also wrote it’s quite difficult to find PCB’s that are worth redoing, and for small production runs it’s probably not worth to redo the PCB’s. Part of his motivation is also to introduce himself to new companies and build trust to do future designs for those companies.
That’s pretty smart…
FWIW, why not shift the two vias at the left a little to the left to open up a path between the upper/lower GND sections there?
1 Like
Reference? That would allow high frequencies radiate from noisy to sensitive part. That’s exactly what we want to avoid.
1 Like
I was thinking that the point of isolating them was to isolate them, adding a cap between the regions would eliminate that isolation.
I can’t say if what you suggest will be better or worse.
Better - because you have connection you mentioned.
Worse - if return current (for vertical tracks) travels in green copper than here will have to get out of the way more.
Which way it really travels would need to look wider on PCB. May be the connection at red (brown) on the right is enough.
There is an argument todo this and that is EMI. By placing a 500V+ capacitor in that place you can control where the EM will flow and is a recomended practice.
Its a bit like that bottom-right mounting hole which is isolated from the local planes (because they are isolated). I would provision a high resistor (1MR) and maybe a capacitor to provide a high-frequency tie.
Also there is an argument for going 4layer and that is again EMI as you have created a few gap antenna’s.
These would only really be of concern if you were to take this to product
They are known as “stitching capacitors” and it is the recommended way of joining two planes together AFAIK.
Also needed for high speed signals changing layers:
I had not looked at the isolated section before.
It is also completely hidden in the schematic.
All those weird boxes around schematic sections do not clarify anything, but just obfuscate in the way they are uses.
It would be useful to make it at least clear there is an isolated section in the schematic, drawing a single box around the isolated section may be a good idea to put more emphasis in this. By selecting parts on the isolated section of the PCB I found what parts belong to the isolated section:
You’ve put the SMPS module at the edge of the isolated section, but you put the I2C isolator smack in the middle of it and this increases capacitance between the GND plane an the tracks non-isolated section. If you look at the pinout of the I2C isolator (U8 ISO1540DR) you’ll see that all the pins on one side of the IC are for the “non” isolated bus, while the “isolated” bus has all the pins on the other side of this IC. This chip is designed specifically this way to make it easy to make the IC itself bridge the isolation gap.
Sometimes (high voltage) capacitors are used across such isolated bridges to get a defined capacitance. If there is no such capacitor then very likely the parasitic capacitance in your SMPS module (RFM-0505S) or the I2C isolator (ISO1540DR) dominates, and high AC voltages over the gap could disturb proper behavior of these parts.
I’m not sure what would be the best option in your application. Maybe you can get some guidelines by reading the application notes for your SMPS module or I2C isolator.
Oops, I missed the change. This tread is getting quite long, and I was still working with the first iteration of your PCB.
The “main” I2C bus (SDA & SCL) do have pull-up resistors (though they are very hard to find on your schematic) but the “isolated” bus (SDA2 & SCL2) does not have pull-up resistors. Are these forgotten, or are they on the other side of the off-board connector.
It is more common to remove the “ohm” part for resistors, and just print the value as “10k”, which fits nicely in the area of the resistor itself with no overlap.
I may have already written it in one of the first post in this thread but I find the schematic very hard to read (and not only because of the blue boxes).
There is not much use in changing your (presumably working) schematic now, but for your next project, try to use much less labels and more wires and adhere to logical rules such as voltages go from top to bottom of the schematic, and signals go from left to right. and mage logical groups of parts that are related to each other.
Maybe you’ve already changed this. This comment is also based on the first iteration of your project.
1 Like
Nope, I actually missed that. I’ll have to add that in.
I’ve also de-tangled your LED driver circuit (Voltages top-down, signals from left to right):
It does need a bit more paper space, but it makes it instantly clear how the circuit works. I also noticed you use R_small and I do not like this resistor much. with the normal “R” you can place the value inside the rectangle and this saves more space then you gain with using R_small and placing the value outside the rectangle.
A 10k resistor results in a quite low LED current, but it’s probably still visible. The other resistor (R15) is only for defining a gate voltage when the outputs of U13 (PCA9685PW) are in high impedance, ans I assume (have not checked) they are so just after startup.
Using R16 as series resistor for the FET does lower it’s switching speed and also protects U13 (PCA9685PW) in case the MOSfet gets damaged, and this is good, but with R15 and R18+LED) you’ve also created a voltage divider on the Gate of the MOSfet. For the current configuration it does notmatter much but when you lower R18 to get more LED current it may become an issue (Although Ugs of the AO3400A is quite low). By connecting R16 directly to the Gate you circumvent the whole issue.
1 Like
Quoted from design-4-emc website referred above:
A stitching capacitor provides a path for return current to flow back to it’s source. The capacitor would connect between the ground plane and power plane
Not between GNDA and GNDD, but between e.g. positive power plane and GND.
and must be located adjacent to where the signal trace changes reference planes.
Not just anywhere. Routing a track so that it jumps over the gap between GNDA and GNDD isn’t what we want.
On the last revision, I removed those indicator LED’s from the LED driver mosfets.
Can I clarify, what is the purpose of the isolation in this case? Do you need galvanic isolation (i.e. no DC path from one side to the other)? Or is there a different reason?