Hmm, I have made a lot of footprints and dutifully place pin 1 in upper left corner, made steps to match, and went about making boards. Some of them I just hand-soldered and never generated a placement file. Some went to jlcpcb for assembly and I sent the placement csv (massaged into their trimmed-down format, but original x/y/rot numbers). They built the boards according to orientation on the silk and never told me if they needed to fix anything, but I think now that they must have fixed some rotation problems. I am now prepping files for my local assy house, and have rotation errors.
Executive Summary: Instead of building footprints oriented with pin 1 in upper left (which is correct for a lot of parts like soic/msop/vssop…) I think it is really needing to be in the orientation as if you are viewing the component sitting on the tape with the feed sprocket holes on the left side. Or is there a setting that defines part orientation with respect to the tape that I have not found?
So I tested this with my library, but as an example: all of the sot23-3/5/6 parts in the kicad library would be off by 180 degrees, since pin 1 is on the opposite side from the sprocket holes, and those footprints should be rotated by 180. I verified this with a 2N7002 from the kicad lib – should be rotated by 180 to match the tape.
Here is a TI part tape showing pin 1 next to sprockets for soic/vssop and opposite side for sot23/sc70:
Which basically says just let the assembly house deal with it. Still seems like the footprint convention should be to match generally-used orientations on feed tape.
Is pin-1-upper-left still the current advice? Anyone have assy issues due to rotation or do the assembly folks just fix it as needed?
Pin-1-top-left is the IPC industry standard convention, which the KiCad libraries follow.
The issue with JLCPCB’s convention (basically, pin 1 oriented as the part comes off the reel) is that the orientation is part-specific, not footprint-specific. Therefore it’s impossible to set up a library that matches JLCPCB’s expectations for orientation without making a unique footprint for every part.
That’s why JLC provides a preview of the board with your orientations so that you can spot the discrepancies and resubmit a corrected CPL file. But they will fix it if you don’t. They also spotted my use of a smaller SM part than suitable for the pad (my mistake choosing the part). So they are on the lookout for such problems. But I also provide hints like a silkscreen dot near pad 1 of ICs to help.
