I have a question on pin numbering order, as per Library Convention S4.2.2: why is order from top to bottom?
Maybe in some electronic schematic rules there’s a common recommendation that I’ve never heard of (or I don’t remember), and someone can address me to that.
I find it quite awkward, you know, I’ve always been counting floors in a building with positive numbers ground to top. The same is natural to me with cartesian axes.
The only reference that comes easy to my mind for top to bottom positive counting are pixel coordinates on screen/DIB/BMP files. That belongs to older CRT screens, and their line scanning order, I can understand it.
There are some other awkward counting standards, like Xilinx’s own reversed bit ordering – and that is even more strange, from a company that should know counter bits can be counted with powers of two…
Over time I’ve also shared schematics with many different designers that agreed on another convention, that I understand it’s hard to make a rule of.
With relevant and complex IC parts, let’s say over 20 pins, and physically arranged in two lines (like SOIC) or on four sides (like QFP, QFN, etc.), we kept distribution of schematic pins as in the physical package. That helped a lot verifying a board under test or a PCB routing with schematic.
Any opinion on this?