That would be possible with some simple house-keeping -
ie avoid using the same Ref’s for Analog vs FPGA, avoid automatic-net names, & take care to match where it matters (3v3).
Most CAD tools allow NETLIST ‘OR’ operations, where multiple netlists can be imported/merged into one PCB.
Revisions can get a little trickier with that flow, as some vary behaviour on First vs Subsequent imports.
KiCad looks better than PADS in that aspect - in the test I just did, kiCad allows rename net by Import & even managed a fractional import
Clearing component “J9:/5080DB5C” pin “2” net name.
Changing component “J9:/5080DB5C” pin “5” net name from “NJ9B” to “NJ9C”.
Changing component “J9:/5080DB5C” pin “9” net name from “NJ9B” to “NJ9C”.
(Here J9.2 was NJ9B, but not present in revised NJ9C netlist)
Like you, I want to use a text editor as well. A schematic-specific language would still be text-based and editable with a text editor. But it would also be able to do error checking, support hierarchy, and allow easy refactoring of the circuitry. Just editing the netlist doesn’t. It’s like the difference between writing machine code or writing Python. The main advantage of editing the netlist is you can do that right now.
The advantage of a hybrid method. Make the root PHDL and allow sub modules that are actually schematic pages. It would have to be that way round due to the impracticality of hierarchical sheets with very high numbers of connections
Cross probing still works, either pulling up a schematic sheet or highlighting the PHDL line
I have really enjoyed your story My profile has very little to do with the one you describe (basically I’m a one man band doing very small jobs), but it’s really interesting to hear your rare experience of a professional business going that way for proper size projects and the pros and cons involved.
As an exercise, for creating PCBNew NETLISTs using Scripts, I first looked for the minimal information content that would still load components into PcbNew.
Turns out, that is quite a lot removed ( & an editor with brace balancing helps the quick checks here )
Example attached, if anyone is interested.
I think it’s a real shame that PCBnew still requires information like timestamp and (more annoyingly) one absolute path, but it’s great to know where we stand.
Oops, do you mean the design( section I have in there ?
I left that in, as I consider that souce, date, tool useful minimal audit information, but I’ve just tested if it is mandatory, and it still works fine with design() sub-block removed… (ie no timestamp or absolute path)
Na, @Andy_P was thinking of (tstamp 56FD43D6) fields within (comp ... ) brackets.
But even your first file is missing them, so PCBnew doesn’t insist on them apparently?
Would be interesting to know what happens when you do an import in pcbnew with this option activated:
Btw, while you guys are solving riddles there, I got a problem I couldn’t solve the other day - how to add extra fields to .sch files so they stick when one safes the file in Eeschema? @devbisme 's KiField must master that somehow (didn’t test it yet as I didn’t had time).
OK, here is what I did:
open any .sch file and add an extra field to a component in a text editor and safe it
(in my case I added an F 6 field and put in “_” as a placeholder for the information, copied the F 5 line more or less)
start KiCAD/Eeschema and load that file and then check the component’s properties for that extra field - it was gone
safe the .sch file and the line also vanishes from the .sch file
adding the extra field “_” via Eeschema’s component properties dialog funnily does create the same line again (when the file is saved) but this time the field sticks and doesn’t vanish
… I modified .bak files, the .lib symbols also got the field later on, changed standard field in Eeschema to have this one as 6th… but nothing of that helped. All in all just mentioning it in case you need this functionality in your endeavors in case you need/want to create .sch files down the road for visual inspection/check for some of the stuff.
Correct. They are not required for normal NET import.
I would expect issues…
I flipped to TimeStamp, and for a file with no timestamps, it actually almost/sort-of worked…
Reports attached - looks close, but the cursor had only a single C attached.(ie many parts lost)
Script (.bas) can run in either PADS SCH or PCB, in Eval mode, and exports a KiCad .NET file.
This does not try to be ‘too clever’, it extracts the nets, parts, refdes, and tries to label correctly.
A simple ASCII file is the transfer point between the two.
Script adds a KiCad_footprint attribute field into PADS database, & has a mapping table to fill this in.
Actually worked first time (amazing) - All looks good, even the error messages make sense.
Part labels need to flip between values and parts, which they do.
PADS net list uses A-K for LED and kiCad expects 1-2,
Y1 has 1.2.3.3 mapping, illegal in PADS, which has 1.2.3.4
In this case, 3&4 are gnd so it makes no difference.
Target uses are
Using PADS SCH Eval-mode to create many (smaller) SCH, to one large kiCad PCB
Commercial users can evaluate kiCad in parallel with PADS whilst evauating high license fees…
Employees can do private jobs
Some parts of the company can use KiCad instead of PADS
KiCad users can train in PADS, to bolster their CV’s
Next info that would be nice to pass over, would be placement XYR, but the kiCad NET format has nowhere for that ?
No, don’t think so.
That’s what I get when I hit production output pos file in PCBnew for the test project up there:
### Module positions - created on 28/06/16 15:55:20 ###
### Printed by Pcbnew version kicad (2016-03-04 BZR 6608, Git ba038ac)-product
## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
C101 C_100n-16V-X7R-kemet_0805 C_0805 162.5600 -76.9620 0.0000 top
C102 C_100n-16V-X7R-kemet_0805 C_0805 155.9560 -76.9620 180.0000 top
U101 LDO_MIC5205-3.3V_SOT23-5 SOT-23-5 159.2580 -76.9620 180.0000 top
## End
Or did I misunderstand your XYR reference?
Though PCBnew won’t be able to read/import that anyway, so you’d have to look at the .kicad_pcb file to get those moved with all the implications - eww.
As for my (unrelated) problem… I’m running BZR6608 on Win7 64bit atmo… might need to upgrade to the latest and see if this persists.
No you are correct. PADS has an ASCII (undocumented?) feature where you can add XYR to the ascii line, and that is used as initial placement suggestion. Re-import ignores that (as it probably should).
Another approach would be a script that can move parts once loaded, but that then makes this a 2 step process.
Yes, such placement files will be widely available, from almost any other EDA flow, which is why I was looking for a means to apply that info.
Digging about in your examples, and using the references here & some google, my learner Python comes to be this
import sys
from pcbnew import *
pcb = GetBoard() # Read loaded PCB design
RefNm = ['U1','U2','J1','J2'] # Lists of Ref X Y R M to apply to just imported netlist/coarse placement.
RefX = [7050.0,7050.0,6400.0,6400.0]
RefY = [4700.0,4100.0,4100.0,5250.0]
RefOri = [0,45,90,135,180]
RefSide = [False,True,False,True] # Flipped is True for Bottom
# Scan the lists test - Requires lists of RefNm, RefX, RefY (mils), RefOri, RefSide, & scans to apply those to the parts.
for Idx,Rn in enumerate(RefNm):
print "# RefNm:",Rn," ",RefX[Idx]," ",RefY[Idx]," ",RefOri[Idx]," ",RefSide[Idx]
nPart = pcb.FindModuleByReference(Rn)
nPart.SetPosition(wxPoint(FromMils(RefX[Idx]), FromMils(RefY[Idx]))) # Update XY
nPart.SetOrientationDegrees (RefOri[Idx]) # Update Rot
if RefSide[Idx]!= nPart.IsFlipped(): # Current Side <> Reqd Side ? then flip
nPart.Flip (nPart.GetPosition())
print "Press 'B' when done, to refresh display & copper"
which is quite compact.
Seems to work, tho display refresh seems variable, & read-back checks seem ‘sticky’.
Next is to try & see if there is a PcbNew command line method to
a) first load a NET file then
b) run a Python script (above) on that loaded data set.
