PCB with KiCAD: Possible error in routing decoupling capacitors

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I was inspecting my work with my first pcb in KiCAD.

I was looking at the 3d model, and i was checking out the three decoupling capacitors i have placed.

And then i noticed that they do not actually connect with an IC (no trace).

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Of course, i made sure i routed all the ratsnest properly - and there are zero unrouted.

These capacitors, like i said are decoupling capacitors. This means one pic is connected to Vdd and one to GND of the IC.

But the Vdd of all the ICs is the front copper plant (5V) and the GND of all the ICs is the back copper plane.

My caps connect to the front copper plane and the back copper plane and that’s it. No connection to ICs.

But, since the ICs connect to these planes, in order to get their power and GND connections, the ratsnest check is satisfied, and that ratsnest is cleared.

But i see no actual connection of an IC to one particular decoupling capacitor!

Isn’t this like now there are three 100nF capacitors in parallerl between the Vdd and GND? So isn’t it like one 300nF capacitor that between the two planes, that all the three ICs share?

Have i done something wrong?

I also post pics of the schematic as an example and the actual pcb

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The software is working just like it’s supposed to. It doesn’t (moreover: can’t) know the purpose of the capacitors. The exact position of the wires on the schematic and where they connect to doesn’t matter for a netlist. The netlist is just a list of groups of things connected together and that info gets transfered to the PCB.

You have to keep the purpose of the capacitors in mind when placing the footprints on the PCB. If you go around placing them willy nilly you this is what you get.

I see that this is the same board that was reviewed in Review of my first board. @paulvdh probably asked you if you have decoupling capacitors on there just for this reason.

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Read Does the connected trace to VCC matter here? and the threads linked from the first post of it.

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(now it should include a link to this thread, too)

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First of all, I agree with the comments above. Also…

Typically when I lay out a board the first components I place after the ICs are the bypass capacitors as close as possible to the Vcc and Ground pins. I think that placing bypass capacitors as an afterthought tends to be a common error for beginners.

And finally…are you using radial leaded disc ceramic capacitors for bypass? This seems out of date. Leaded disc ceramic capacitors have more lead inductance than MLCCs. That is more of a problem for today’s faster/lower voltage circuitry.
I learned that they are not so good for modern pcb assembly. I once designed some into a power supply and after manufacturing they were sort of flopping either way. The manufacturing engineer was crimping the wire leads to lift the capacitors above the “lead flash” or ceramic lead coating close to the body. This made assembly very messy and also increased stray inductance.
Also these disc ceramic capacitors do not give you as much capacitance as you can get in an MLCC.

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First, when you have your components in PCBNew, you take care of the critical stuff. Mostly (If you’re not routing complex processor or FPGA Boards) these are High Speed lanes like USB differential pair and second on the list of course are decoupling capacitors.

Best Way is placing the pin of the decoupling capacitor which is connected to +VCC right NEXT to the +VCC pin of the chip needing this capacitor. As close as you can place it!

Next, you have to see that the pin of the capacitor connected to GND, is connected there by the shortest path possible, best a VIA to a ground plane on a bottom layer (Copper fill), so that you have no unnecessary inductance loops.

Only then you take care of the rest.

And yes, completely agree with @BobZ about the MLCC.
(Unless you’re reconstructing a Vintage Commodore 64 circuit and need those TH LD Ceramic capacitors :smile: )

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there is nothing wrong with trough hole parts if he has them in stock, for one they have less issues with microphony if used in signal path in comparison to surface mounted, only issue here is he is thinking kicad should show all nets like in schematic sheet but as people above pointed out that is not the case, and i think all cad software use same behaviour here.
you need to prioritise your layout, first bypass caps, then feedback stuff where loops should be kept small and then rest.

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Thank you! Ok right next to the IC. But the GND pin of the cap, is connected to the GND plane and not the IC…

My question is… The Vcc pin of the cap… Where should it connect?
Should i draw a trace to the Vcc pin of the IC?
Or, should i draw a trace to the Vcc plane?

(i have the bottom layer as GND and the upper as Vcc)

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The GND pin of the capacitor should be connected with a VIA to the GND Plane. Forget the GND of the IC.
The VCC of the capacitor should be connected with 2 things: a trace to the VCC of the chip (shortest possible), and a connection to the power plane (top side) (or a via to the power plane if you have a >=4 layer board).

Sometimes chips have a GND pin next to their VCC pin (like many STM32), then you can have the decoupling capacitor parallel to the chip , with both pins connected to VCC + GND of the chip and through vias or copper fills to their respective GND and Power planes.

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Here is how I do it at 2 layer PCB (bottom is GND plane):

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Following VCC tracks you will find 4 decoupling cups.
At 4 layer PCB I would not have VCC track but connect each of IC VCC pin by via to VCC plane like here I did with GND.

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