For example in some cases it could be beneficial to only have connections (solder points) on the top and bottom layers to be able to more easy service/disassemble/assemble some through hole connectors. Is this possible to do in the PCB footprint editor, or how? Or is it just stupid?
I don’t understand if you want to have:
- pads with NPTH in them, or
- pads with PTH in them, but not connected to internal layers.
I mean a pad on top layer, with a “valve” going to a pad on the bottom layer with no pads/connections to the copper on the second or third layers. This to be able to more simple solder/desolder some connenctors. Or is it nothing to gain here?
If copper on the inner layer will have different net assigned than your pad it will be automatically not connected to your pad.
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You can use: PCB Editor / Tools / Cleanup Unused Pads to remove the annular rings on layers that have no connection. You can not do this directly in the footprint editor. A footprint does not know how many layers you have on your PCB. Maybe at some time a full padstack gets implemented in KiCad (then you can use different shaped pads on different layers), but at the moment this is not supported yet.
For instance it’s possible one or more pins, which I want this behaviour on, is on net GND, which actually may be a complete inner copper layer which I want GND to be connected to other components/pins which are not “service” components like connectors.
In such case it have to be not complete near the pads you want being not connected.
I think you can place rule area to remove GND zone from some region.
What is that and how to do it? Remember I still in this GND case want the GND to be connected to top and bottom layer (1+4) and no GND connected to layer 2 & 3.
At right just under symbol to place zone you have symbol to place rule area. You can specify what is forbidden (like zone filling) in that area. I think rule area can be specified for what layers it is. I will not ensure myself if I’m right. It is 22:25 here and I am still at work. About 21:00 I switched off PC with KiCad. And before going home just found some mails I decided to answer and then took a look at KiCad forum…
Thanks but sorry if I don’t understand or find where this is to be set.
I think you may be looking for thermal relief connections to these pads on inner layers. These are defined in the properties of the copper zones that fill the inner layers.
Pad connections in the zone can be set for Solid, Thermal reliefs, or None. While none is technically what you asked for, I suspect you likely want thermal reliefs which will make electrical connections from the plane to the pads, but those electrical connections are not good thermal connections so that they do not hinder soldering or desoldering pins in those pads.
I mostly tuned out of this thread because I do not understand what TheSwede (OP) 's intention is. Maybe a better explanation helps to get better answers?
In other words, chosen pad layers for a specific component should be possible to release from the net on top and bottom (or whatever preferred layers).
It’s all about:
• What you want to do
• Your knowledge of Kicad
• Your Settings
I recommend Trial & Error testing/playing-around
Image below shows THT PinHeader, THT/SIP, Connector-Pin and Mixed Net’s. Your setting will most likely give DRC/ERC Error and may not connect until you change the settings and/or DRC/ERC and Interactive-Router settings.
If I understand correctly (and, I may Not understand correctly) Nonetheless, as you see what I think you want is fundamental Kicad knowledge…
Mixed, Un-Mixed Nets on THT connections and Traces…
2-Layer PCB
4-Layer PCB Mixture of Pad Connection Layers…
I guess it’s difficult to comprehend what you mean with this picture:
because there is absolutely nothing remarkable about it. It is completely bog standard and KiCad produces PCB’s like that without doing anything special.
And therefore, the questions still remains, where is the mismatch between your thoughts and your post.
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Ok, I don’t know what to say so let’s cancel this topic.
I guess there is still a mismatch between your expectations.
I suggest you draw something similar in KiCad, make a screenshot in the 3D viewer just like BlackCoffee did, and if there is still some part you don’t understand, post your expectations and the observed result, (and the differences between them). If you have a concrete question, we can answer it.
There’s no need to cancel anything, but you could tell for example what means:
I can only guess based on this and your other posts that you might want to solder THT connectors manually and want to prevent too much heat dissipation away from the solderable surfaces. I also guess that copper pours/zones/planes are the problem, not ordinary tracks. If my guess is correct, the only situation when they may be a problem is with GND/power planes and the corresponding pins. In that case I can say this:
KiCad doesn’t have pad stacks, i.e. pad geometry and rules per layer which could be made with dedicated UI. To prevent zones filling to inner layers of a THT pad you can draw a rule area (formely “keepout area”) in a layer and set it up to prevent zone filling inside that area.
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“I also guess that copper pours/zones/planes are the problem, not ordinary tracks.“
Yes!
“the only situation when they may be a problem is with GND/power planes and the corresponding pins.”
Yes again.
“To prevent zones filling to inner layers of a THT pad you can draw a rule area (formely “keepout area”) in a layer and set it up to prevent zone filling inside that area.”
Ok, how to do that? – I found it, thanks for good help.
