Passing busses from parent to child and back again

Hello All,

The problem is similar to the topic below, but I have bidirectional lines in my bus. Using the same name guaranteed by copying and pasting the signal names does not provide any joy.

I’ve looked at this thread and done everything short of using global net names, but the connections don’t get connected.

As with the thread originators in the link above, my schematic is nonsense beyond illustrating a point. (25.5 KB)

Thanks in advance.

I simplified your schematic a bit.
If I just carry D[0,7] over the bus, then it works, and the ratsnest appears in Pcbnew (after [F8]).

Note I also used the bidirectional hierarchical symbol, so that is not the issue.

Your problem is in combining the **Name[0…123] with the other signals.
If you read the Eeschema user manual, chapter 6.5.3 then:

It’s one of those odd ends in KiCad that still needs some fixing.
It may have been fixed in the current nightlies, but I have not checked.

It is fixed in the nightlies (not that I’ve used it yet), and is one of the things I’m really looking forward to in v6 when it lands.

I did a quick test after SemazuruCDE’s remark it should have been fixed in the nightlies.

so I opened the dummy project in my current nightly (maybe two days old) but it does not work as expected.
I get a single ratsnest line in Pcbnew, but that is from a single connection I added deliberately to verify if ratsnest lines are shown at all:

I even deleted the hierarchical pins on the Master sheet, and re-imported them from the two sub sheets, but to no avail.

To OP:
Nice you made an example project, but it’s easier for you and others to keep such examples small & simple. A design with just a few pins is easier to draw and quicker to verify. (Although it does not matter much with KiCad’s auto-repeat with the [Ins] key. I also get for example several hundred messages about single net pins.

The syntax in nightly would be {LCDIN[0..7] LCDOUT[0..7] D[0..7] R~W} not LCDIN[0..7],LCDOUT[0..7],D[0..7],R~W as in the original design

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You might need to specify the bus name differently. I remember seeing a bunch of traffic here about this very issue on the nightlies, so searching the forums might be advised here.

EDIT: or… just read what @craftyjon said while I was keying in the above… :wink:

I’ll look at it, and type along as I go…

First things first. Why didn’t I run an ERC in KiCad-nightly?
So I did that.
ERC gives lots of errors so it knows there is something that does not work, and that is good :slight_smile:
Saved the ERC report, opened it in a text editor and pasted an excerpt here:

[net_not_bus_member]: Net /sheet a/LCDOUT7 is graphically connected to bus /sheet a/<NO NET> but is not a member of that bus Severity: warning
    @(2000 mils, 4600 mils): Bus to Wire Entry
    @(2000 mils, 4100 mils): Vertical Bus, length 100 mils
[net_not_bus_member]: Net /sheet a/D0 is graphically connected to bus /sheet a/<NO NET> but is not a member of that bus Severity: warning
    @(2000 mils, 4900 mils): Bus to Wire Entry
    @(2000 mils, 4100 mils): Vertical Bus, length 100 mils

(It would be nice to be able to copy from the ERC check window itself…)

After that I tinkered a bit with those bus names. Removed the commas between net names and put the whole thing inside curly braces as craftyjon suggested. and ran ERC again. Almost all errors / warnings are gone, which is of course a good thing. There is one error and one warning remaining. It is for a wire entering the bus, but it’s not labeled. Good thing KiCad catches this too!

Fixed it. Ran ERC and the window stays empty (no screenshot :slight_smile: )

Then [F8] and lots of ratsnest lines in Pcbnew:

It’s about 3 bundles of 8 wires and the odd “R~W” also thrown in.

So it works as expected, all Hail to the KiCad team.
To be fair, in my previous attempt there was a missing footprint for a QFP100 14x14 p0.5 so I replaced that with a similar footprint from the V5.99 libs.

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