Off schematic connections and ratsnest


#1

Hi, being a newbee to Kicad I have a problem describing to Kicad the presence of off schematic connections. E.g. I am developing a simple electrical interface board which has multiple connectors.
On several of these connectors the signals (say “DPS1”) are duplicated (off board). I can’t seem to inform Kicad (tried all kinds of global and hierarchcial labels) that when routing I can choose freely among any of these connector pins for the valid electrical connection. The router always seems to want me to connect what seem to be identical net pins together on-board although they are already connected off-board ?

I hope I’m clear in my question, seems a standard requirement to me.

Thanks.


#2

Of course, everyone regards their own requirement as “standard” regardless of whether it is or not. :slight_smile:

KiCad has no knowledge of off-board things, and there is no way to tell it. If you want the nets to be treated separately, then create separate nets.


#3

Hi Bob,
sorry but that is just the point, I “don’t” want the nets to be treated separately I want them to be globally understood (within the schematic).
If connector J1-3 has net “DPS1” assigned to it and connector J2-1 also has net “DPS1” assigned to it then why does the rats-nest want me to connect J1-3 to J2-1 onboard (as well as to the other components which I do wish to connect DPS1 to naturally). I would have thought that my connecting the components to J1-3 or J2-1 would satisfy the routing logic ?
Being a newbee I can’t exclude the possibility that my description of the connectors (and net indicators) may be faulty and has confused the netlist but if so how to I detect this (visually both traces show DPS1 identifiers as expected).


#4

Well the fact is it doesn’t!

KiCad has no knowledge of off-board connections… if you want to keep KiCad happy a workaround is to draw a connection on an unused copper layer.


#5

Err, no…
The netlist is considered tasks for the router to do, it connects same-names with traces.
It has no clairvoyance, and no way of handling what you think are off-board vs on-board.

Usually, you will have a trace tree and just one connection to each of J1-3 to J2-1 - as you route, connections can re-order.

Things get tricky if you have multiple board sub-panels, and one sch, and you effectively want to include the wire loom into the PCB design. This sounds more like your case ?

One work-around I’ve seen for that case, is to allocate extra/spare PCB layers for the ‘virtual loom’.

ie between-board loom is routed carefully only on those layers, and this will pass connectivity tests, and you actually plot fewer layers (omit the wire loom layers).


#6

Well thank you both for the workaround suggestions and clarification.

I can’t help feeling that there is something missing from the tools in this respect (seems like a very simple and common concept, akin to the requirement for externals in programming) but don’t get me wrong I am in great admiration of the capabilities of Kicad and the effort put in by so many to refining the software.

Ours is not to reason why etc.


#7

I think the problem is a conceptual one.

The purpose of a circuit board is to join things that are not otherwise connected. If you tell the tool A,B,C need to be connected, then the tool assumes that there needs to be copper track connecting A,B,C on the circuit board.

If in fact, you are telling the tool that A,B,C are already connected then no tracks need be created, and in fact there is no need for any copper tracks at all, perhaps just some mounting holes. (e,g A and B might be legs on a component which are internally connected, A and C will be connected by a wire jumper, B and C are separately connected to a telephone exchange which links the two together).

There are some rare cases where it might be desirable to make use of “hidden” connections, but equally there are many cases where you must have all the pins connected, e.g. GND pins on an IC are internally connected, but you must connect them all on the PCB. Rather than add complexity to the tool to try to describe all the possibilities, it’s a lot easier to use some human intelligence. You know what you are doing better than the computer does!


#8

Oh I entirely agree Bob that the use of human intelligence is desirable especially in applications where AI has still some progress to make (travelling salesman etc.) I still make great use of “Assembler” in certain programming tasks =:o , it just gets the job done as I wish it to be done.

Which is why I naively assumed that there must be some elegant way of informing the router of conditions (electrical connections) which it could quite naturally not know about as they are outside of the scope of this PCB. I mean connectors are for connecting to “off-schematic/board” elements, the idea that each pin of the connector is going to a single unique element goes against reality especially when the elements are power supply lines where it makes sense to spread the current over multiple pins/connectors for design robustness.

The idea that I cannot “easily” inform the router, that it doesn’t have to run a power track to a connection pin on the far side of the PCB as there is another pin on another connector (electrically equivalent) located just beside the element to be powered that will do just as well, defeats me. As this is my first PCB on any tool chain, it left me with the idea that I must be making a usage mistake of the net labels or something.

Apologies to all if I am flogging a dead horse or being pedantic on the subject.


#9

There is, draw the schematic based on your knowledge of what you want to achieve. Also, never make assumptions :wink:

KiCad is a tool like any other, there are limitations. We can you tell you the best ways to use it, but we don’t have a magic wand to make it work the way you expect. Accept it and move on to productive use!


#10

Which is exactly what I am trying to do Bob and my reason for posing the question on the forum. How do I describe correctly on a schematic elements (connections) that are by nature off schematic in such a way as to pass this information correctly to the router ?

And the circle is complete !


#11

Give the nets different names, like DPS1_A and DPS1_B. Anything that has the same name is assumed to be connected on the PCB. Place a text label on your schematic that notes that the two nets are connected together off-board if it is helpful.


#12

As I wrote in previous posts, create separate nets, or draw a connection on an unused copper layer… Or simply ignore the DRC…


#13

Yes that’s what I have done on the schematic, it just seems clunky and defeats somewhat the usefulness of the ratsnest.
When I get a bit more confident with the tools I may try to add the virtual copper layer as PCB_Wiz suggested if there aren’t any better ideas (and if someone doesn’t eventually add a virtual trace component/feature). Just at the moment I am trying to limit the effort to reusing partially an older routing card (in the 3 card stack) done by someone else.

Thanks to all.


#14

If you really want to use the ratsnest to tell you that two distinct nets are actually the same, the best way is to ignore the DRC error and leave it unconnected. This is not recommended practice, but you are free to do it! Unfortunately KiCad does not have a good way (yet) to mark a particular DRC error as permanently ignored, so you’ll just have to know that when you run DRC you should expect an error.


#15

The general rule is a netlist connection WILL BE ROUTED.
It is common to join all (eg) GND nets, in all PCBs of a stack, even though, in theory that can have redundant connections.

PCB traces come for free, do not be afraid to have more than the minimum !!

The flaw in your approach of assuming GND pins all somehow, magically, find ground externally, is what if someone applies that rule to ALL boards in the stack ? Oops.
Or, how does someone trouble shoot a partial stack ?
Not to mention, from a design viewpoint, it is better to have shorter, lower inductance common connections, and wires are not always 100% reliable…


#16

Is there a way to add a schematic component and toggle a flag or something to say that it is not connected and should be left out of the netlist?

If this was the case then it might allow the addition of components in the schematic (or possibly the pcb) and have it considered off-sheet.


#17

Err, not really in my opinion, they come at the expense of board area and routing complexity of other traces.
Where both (quite limited physical board area and manual routing in my case) are in limited supply, you like to avail of every shortcut to finish the PCB quickly, efficiently and with a minimum number of layers.


#18

I’m not assuming, I know from the other board/s in the stack schematics, but I would like to pass that knowledge at least in part to my own interface PCB project board.
Naturally if you give erroneous information to the router GiGo.
I thought there was a preference for a “Starred” ground rather than a “Ring” ground to avoid/minimise potential current circulation anomalies ?


#19

That’s true for (eg) special, high sensitivity analog-cases, but modern PCB design tends to be 4+ layers with poured ground planes, to keep power plane impedance lowest, and to reduce RFI generating loops.

and when one or more boards are removed for testing, what happens then ?
Have you carefully covered all combinations ?


#20

I’m trying to hold 2 layers with 4 different supply traces (each with multiple arrival points), this is an interface board designed to interconnect 2 other functional boards electrically and physically. There isn’t a lot of electronics but there are a lot of signals to be interconnected in a relatively small space with considerable exclusion areas.

You mentioned testing difficulties several times but I fail to see the importance, normally testing is done with an intimate knowledge of the board usage and configuration thus any shortcuts (multiple external supply points in my case) would naturally have to be replicated in a functional test rig. Nothing strange to my knowledge in that, you wouldn’t normally try to functionally test any other PCB with only half the supply (assuming there are multiple) lines connected would you ?