Off schematic connections and ratsnest


But the ratsnest is there to make routing easier. But you don’t want to route the ratsnest, so I think you misunderstood what makes a ratsnest useful.

I am interested in seeing what you are trying to accomplish in practice. Why do you include off-board connections at all? If you have two PCBs connected by harness, I would make one project for each of the PCBs. And If you have an absolute need to have a schematic describing the system (both PCBs connected by harness), make a third schematic where you also have made two footprints of the two PCBs (or represent them by connector symbols).


Hi Henrik,
perhaps I am mistaken but for me the ratsnest is a map of potential connection paths/points for the traces being routed. It is a helpful orientation suggestion to allow you to manually route the concerned traces. Ideally when you have correctly routed everything they should all disappear n’est-ce pas ?

The two other PCBs exist (and have purpose) in their own right but were not originally designed to connect together. My project is to allow that connection, to fulfill another task for which neither was originally designed. Not wishing to be mysterious about this I will try to upload a few photos but am traveling in the next few weeks so it will have to wait.

As I may have to repeat this process for several other instances, I would like to build a representative virtual wiring loom (of the electrically common elements) that can be imported/copied so that future projects may benefit from this effort (like a library component albeit completely passive). My newbee (to PCB layout) surprise is that this does not appear to be a common/standard requirement apparently. The idea appears to be that connectors pins each connect to a unique off board electrical entity and any notion that connector pins may be electrically connected/replicated (off-board) seems to be foreign to current routing practice !!!

Do I understand you correctly that the “third schematic” will be understood by the router as not concerning the current PCB (i.e. “be aware electrically but do not concern yourself with trying to place/route the components”) ?

Thanks for your consideration of my problem.


Yup, 100% correct, and you have answered your own question.

Given PCB layout is exactly that, it’s unclear why you expect PCB design tools to include virtual wiring loom support.
There is a whole other industry dedicated to wiring loom software, if you want to do it properly.

Designers can and do layout multiple boards on a single sheet, and the norm is to manually leave the inter-board lines as rats-nests, if you want common net names across boards.

A wish-list item could be some special tag on those pin-pairs, to tell DRC they are ok.

Meantime, you can save a report and list unconnected, and write that on the PCB.
eg 6 unconnected, reminding anyone modifying the PCB, if DRC ever reports more than 6, you have issues to track down. ( or, route inter-board on special layers, as mentioned already…)


Exactly my request from the start but I couldn’t (can’t) believe that I am the only person confronted by this situation. I just presumed I was not using the tools correctly and that the facility was already present somewhere.

Slightly more technical follow on question : Where (and in what format) does the routing software store connections/traces that you have already drawn ?
If it has to be hacked might as well go to the source and a quick google still leaves me a bit at a loss as to what file is concerned with holding this intermediate routing state information !


The routing software AKA PCbnew stores the graphical layout of items on the board in the board file. Its formatted as S expressions which is pretty self explanatory if you open it up in a text editor. As part of this file there is a list of nets, each with its numerical code and its name. This list of nets is built from the netlist file (*.net) which in version 4 is exported to disk by the schematic editor and then read by routing software. In version 5 this is mostly passed between them internally without needing to write a file.

Modules (aka footprints) include pads that are numbered, importing the netlist from the schematic editor will match the given nets to those pads, for the footprint chosen for each symbol.

The designer then draws the tracks between the pads, with each segment being attached to the proceeding tracks net. The ratsnest is then calculated again to show the shortest path to another segment or pad of the same net, until a valid copper connection exists between all pads of the same net. As you can imagine the algorithm for this is complex but dynamic enough to be calculated quite quickly.

As such there is no “intermediate routing file” or format, it is calculated from the nets, tracks, vias and zones in the pcb design file.

While it may seem counterintuitive that what you set out to achieve doesn’t work, Its one of those problems where without careful implementation it could quite easily lead to useless boards. Its asking the software to assume something exists for which it can’t verify.


Load the pcbnew file into any text editor, and inspect.

(net 10 VCC)


  (segment (start 129.286 135.001) (end 129.413 135.001) (width 0.25) (layer F.Cu) (net 10) (tstamp 5AAAAE4E) (status 1000000))
  (segment (start 112.141 122.301) (end 128.778 122.301) (width 0.25) (layer F.Cu) (net 0))
  (segment (start 114.220001 137.2125) (end 122.708333 137.2125) (width 0.25) (layer F.Cu) (net 11))

Well, not quite. Your initial request was for the system to be clairvoyant, to ‘somehow’ know which pin pairs are OK to unroute, from the SCH side.

The DRC tag I mention, is a manual operation that is applied in the PCB, and that would give a means where any designer can tell the PCB DRC which errors have been manually checked and flagged as ok.
They would not vanish, but go into a separate basket (eg own colour and count)

I believe the ability to tag DRC is already a request / somewhere on the road map, as that can apply to many things ( eg stubborn or deliberate clearance issues etc). Of course, with such power, comes responsibility… :wink:

You can get close to such “error sign off” even now, I just tried DRC with create report, and a decent text editor like NP++ can compare two files, & highlight differing lines.
ie Compare of a Master DRC base, with a some more errors DRC, does make the differences clear.

A script could do something similar, if you expect a great many lines of DRC to manage.


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