Load the pcbnew file into any text editor, and inspect.
(net 10 VCC)
(segment (start 129.286 135.001) (end 129.413 135.001) (width 0.25) (layer F.Cu) (net 10) (tstamp 5AAAAE4E) (status 1000000))
(segment (start 112.141 122.301) (end 128.778 122.301) (width 0.25) (layer F.Cu) (net 0))
(segment (start 114.220001 137.2125) (end 122.708333 137.2125) (width 0.25) (layer F.Cu) (net 11))
Well, not quite. Your initial request was for the system to be clairvoyant, to ‘somehow’ know which pin pairs are OK to unroute, from the SCH side.
The DRC tag I mention, is a manual operation that is applied in the PCB, and that would give a means where any designer can tell the PCB DRC which errors have been manually checked and flagged as ok.
They would not vanish, but go into a separate basket (eg own colour and count)
I believe the ability to tag DRC is already a request / somewhere on the road map, as that can apply to many things ( eg stubborn or deliberate clearance issues etc). Of course, with such power, comes responsibility…
You can get close to such “error sign off” even now, I just tried DRC with create report, and a decent text editor like NP++ can compare two files, & highlight differing lines.
ie Compare of a Master DRC base, with a some more errors DRC, does make the differences clear.
A script could do something similar, if you expect a great many lines of DRC to manage.