NPTH to copper clearance on inner layers (again)

As I can read in this post, it seems to be going wrong in v8 so DRC errors appear on inner layers in my NPTH footrpint.
Please, can anyone confirm?

The provided link is 2 years old and referred to kicad v7 in a very early development version. This is unrelated to your current stable v8 version.

I would look into the board file, but you have to attach a zipped project in your thread. Not only the board file, as projects ettings and additional custom drc rules may influence the drc behaviour.

Also the complete kicad version (v8.0.x?) is needed for such questions. The used OS version is most likely unrelated to this problem.

I attach a basic test with this violation (152.7 KB)

Updated info:

Application: KiCad x86_64 on x86_64

Version: 8.0.1-8.0.1-1~ubuntu22.04.1, release build

wxWidgets 3.2.1
FreeType 2.11.1
HarfBuzz 2.7.4
FontConfig 2.13.1
libcurl/7.81.0 OpenSSL/3.0.2 zlib/1.2.11 brotli/1.0.9 zstd/1.4.8 libidn2/2.3.2 libpsl/0.21.0 (+libidn2/2.3.2) libssh/0.9.6/openssl/zlib nghttp2/1.43.0 librtmp/2.3 OpenLDAP/2.5.17

Platform: Linux Mint 21.3, 64 bit, Little endian, wxGTK, X11, cinnamon, x11

Build Info:
Date: Mar 14 2024 17:17:31
wxWidgets: 3.2.1 (wchar_t,wx containers) GTK+ 3.24
Boost: 1.74.0
OCC: 7.6.3
Curl: 7.81.0
ngspice: 42
Compiler: GCC 11.4.0 with C++ ABI 1016

Build settings:

Thanks, it’s a good example project and I see your issue. But I was not able to reproduce the behaviour, the PNS router respectfully avoided the NPTH hole on all 4 layers. Tried with current v8.0.2rc testing version (downloaded from Downloads | KiCad EDA, but these are only the windows versions).

However, it reminded me on this older issue with a similar behaviour (PNS router produces track to close to a hole): PNS router creates track with clearance violation (#16879) · Issues · KiCad / KiCad Source Code / kicad · GitLab

As the issue was closed it could be that your issue is also fixed with a current testing version or at least with the upcoming official v8.0.2 version. It would be nice if you could re-test your project.

Sure, I’ll try it again when the next stable version (8.0.2) is available. Thanks for the feedback.

Aahrg… another test project. I’ve got about a hundred of them, and juggling with them is sometimes confusing when following multiple topics on this forum. For the next time, please try to use a uniquely identifiable name (for example by adding your user handle, or the subject of the test).

I am not sure what the problem is. I can open your test project, and the track on the inner layer gets flagged because a clearance override for the NPTH is set to 1mm. (Select track and NPTH, then: PCB Editor / Inspect / Clearance Resolution

The 2 year old topic you linked to seems to address the opposite case. Apparently there was a bug back then and there was no clearance at all for NPTH on inner layers.

I guess that you want your test project to pass DRC without complaints. I assume you want to set different clearances for NPTH on inner and outer layers. (You have not clearly stated what your intentions are, so I’ll keep it at “assume” for now). Best I know this is not supported at the moment. I do understand a feature request for this, as clearance on the outer layers is often needed for fasteners, while the inner layers are protected well enough and only have to deal with the hole itself.

One way this could be done is to have an option to restrict clearance override for NPTH to the outer layers only, and then use PCB Editor / Board Setup / Design Rules / Constraints / Copper to hole clearance for the inner layers.

You also have the option of not downloading the project. Even not answering if you don’t want to.

For me is the same thing

No. I’m just want to know if this is a bug or not. I can live with DRC violations

I think It’s clear. For the NPTH, Is it correct to maintain the copper clearance on the inner layers?

I’m not sure about copper clearance, but you definitely want some clearance to the hole, right? Otherwise drilling the hole would damage the track. Are you saying the DRC uses copper clearance instead of mechanical clearance?

Good point. Yes indeed I’m referring to mechanical clearance. In the Pad Properties I just can set the “Pad clearance” (in my case 1mm) and this acts as copper clearance.

Just to clarify this topic a little more. My intention is to use a NPTH for a screw (for example a M2).

Therefore I have to avoid passing tracks on the layers where the screw head will rest (Top or Bottom). For inner layers there is no such constraint.

I understand. Now I don’t know if there is a bug in KiCad or if it simply works as designed, but for what you want to achieve, you could set the small “inner” clearance as clearance in the pad properties and prevent tracks and other stuff on the outer layers using keep out zones.

Note that you might still want to use a reasonable clearance on the inner layers, as for example the screw threads could dig in a little bit into the PCB and create a short circuit.

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