Ngspice vs Ltspice

I am simulating the same circuit on both simulator with different results.
Please help me to know who is the right result and what to adjust to have the same result.
Thanks in advance.

Kicad-Ngspice



Spice netlist:

title KiCad schematic
.include "/Users/max/Txt/WiperLand/library_spice/anl_misc.lib"
.include "/Users/max/Txt/WiperLand/library_spice/diode.lib"
XU1 GND Net-_C2-Pad1_ /Vout VCC Net-_C1-Pad1_ Net-_C2-Pad1_ Net-_D1-Pad2_ VCC 555C
V1 VCC GND dc 12
R7 /Vout GND 330
C1 Net-_C1-Pad1_ GND 10u
R1 VCC Net-_D1-Pad2_ 10k
R3 VCC Net-_D1-Pad2_ 1k
D2 Net-_D2-Pad1_ Net-_D1-Pad2_ D1N4148
D3 Net-_D1-Pad2_ Net-_D3-Pad2_ D1N4148
D1 Net-_C2-Pad1_ Net-_D1-Pad2_ D1N4148
R2 Net-_D1-Pad2_ GND 4.7k
C2 Net-_C2-Pad1_ GND 470u
R5 Net-_D3-Pad2_ Net-_R5-Pad2_ 100k
R4 Net-_D2-Pad1_ Net-_C2-Pad1_ 4.7k
R6 Net-_R5-Pad2_ Net-_C2-Pad1_ 68k
.save @v1[i]
.save @r7[i]
.save @c1[i]
.save @r1[i]
.save @r3[i]
.save @d2[id]
.save @d3[id]
.save @d1[id]
.save @r2[i]
.save @c2[i]
.save @r5[i]
.save @r4[i]
.save @r6[i]
.save V(/Vout)
.save V(Net-_C1-Pad1_)
.save V(Net-_C2-Pad1_)
.save V(Net-_D1-Pad2_)
.save V(Net-_D2-Pad1_)
.save V(Net-_D3-Pad2_)
.save V(Net-_R5-Pad2_)
.save V(VCC)
.tran 100m  180 0    10m uic 
.end

LTspice

This is not the content of the Kicad forum, because Kicad is not responsible for the simulation operation. In fact, it is ngspice that does the simulation work.

According to my thoughts, the component models used by ngspice and ltspice are different, so it will lead to different results.

If the component model files of the two are replaced with the same, the comparison is meaningful.

Edit:

You may be able to find the answer on the ngspice forum.

https://sourceforge.net/p/ngspice/discussion/

I suppose generating is the right result.
To investigate what is going on you should behave like when checking real circuit. You should check what is at all important points. For example what is at pin 5. I don’t know - may be in MOS 555 versions the internal divider is made with high value resistors and voltage at pin 5 rises more slowly that you expect.

Your output load resistor is different between the models

Please post your 555 model and the diode model.

Diode 1N4148 exctract from diode.lib Orcad

.model D1N4148  D(Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m Xti=3 Eg=1.11 Cjo=4p
+               M=.3333 Vj=.5 Fc=.5 Isr=1.565n Nr=2 Bv=100 Ibv=100u Tt=11.54n)
*$
*
*
* BV, IBV, XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* MEASURED TRR = 10.40NS, SIMULATED TRR = 5.373NS.
*
* RAD: PRERAD
* TEMP= 125
.MODEL D1N4148/125C   D      (
+         IS = 6.42601E-9
+         RS = 0.7520202
+          N = 1.8485649
+         TT = 6.303E-9
+        CJO = 1.75198E-12
+         VJ = 0.4
+          M = 0.2289422
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.8991
+         BV = 1E5
+        IBV = 1.0E-10
+ )
*$
*
* GENERIC FUNCTIONAL EQUIVALENT = 1N4148
* MANUFACTURER = MICROSEMI
* TYPE: DIODE
* SUBTYPE: SWITCHING
* THE FOLLOWING SECTION CONTAINS 3 PARAMETER SETS FOR NON-IRRADIATED
* DEVICES AT VARYING TEMPERATURES OF THE 1N4148-1JTXV DIODE.
* THIS MODEL CAN BE USED FOR ALL OF THE FOLLOWING DEVICES:
* 1N4148
* 1N4148-1
* 1N4148-1JTXV
* THE ROOM TEMPERATURE PRE-RAD PARAMETER SET SIMULATES NEARLY
* IDENTICALLY TO THE -55 AND THE 125 DEG C WHEN .TEMP IS USED.  THIS
* PARAMETER SET CAN BE USED AT ALL TEMPERATURES BETWEEN -55 AND 125 DEG
* C.
*
* PARAMETER SETS EXTRACTED FROM MEASURED DATA
*
*** CAUTION: THE MEASURED TRR AND THE PSPICE CIRCUIT SIMULATED TRR ARE
* DIFFERENT.  THIS COULD POTENTIALLY LEAD TO ERRORS IN CIRCUIT SIMULATIONS
* IF USED AS A RECTIFIER OR SWITCHING DIODE.
*** CAUTION: USE ONLY AT TEMPERATURE SPECIFIED.  ANY DEVIATION FROM THIS
*            TEMPERATURE WILL PRODUCE INCORRECT RESULTS.
*
* BV, IBV, XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* MEASURED TRR = 4.681NS, SIMULATED TRR = 6.544NS.
* RAD: PRERAD
* TEMP= 27
.MODEL D1N4148/27C   D      (
+         IS = 1.27106E-8
+         RS = 0.7546332
+          N = 1.9215823
+         TT = 3.679E-9
+        CJO = 1.72434E-12
+         VJ = 0.3026211
+          M = 0.2
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.998001
+         BV = 1E5
+        IBV = 1.0E-10
+ )
*$
*
* 1N4148
* GENERIC FUNCTIONAL EQUIVALENT = 1N4148
* MANUFACTURER = MICROSEMI
* TYPE: DIODE
* SUBTYPE: SWITCHING
* THIS FILE CONTAINS 3 MODELS AT VARIOUS RADIATION LEVELS OF THE
* 1N4148-1JTXV DIODE.
* THIS MODEL CAN BE USED FOR ALL OF THE FOLLOWING DEVICES:
* 1N4148
* 1N4148-1
* 1N4148-1JTXV
* THE ROOM TEMPERATURE PRE-RAD PARAMETER SET SIMULATES NEARLY
* IDENTICALLY TO THE -55 AND THE 125 DEG C WHEN .TEMP IS USED.  THIS
* PARAMETER SET CAN BE USED AT ALL TEMPERATURES BETWEEN -55 AND 125 DEG C.
*
* PARAMETER SETS EXTRACTED FROM MEASURED DATA
*
*
*** CAUTION: THE MEASURED TRR AND THE PSPICE CIRCUIT SIMULATED TRR ARE
* DIFFERENT.  THIS COULD POTENTIALLY LEAD TO ERRORS IN CIRCUIT SIMULATIONS IF
* USED  AS A RECTIFIER OR SWITCHING DIODE.
*
*** CAUTION: USE ONLY AT TEMPERATURE SPECIFIED.  ANY DEVIATION FROM THIS
*            TEMPERATURE WILL PRODUCE INCORRECT RESULTS.
*
*
*
* XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* MEASURED TRR = 5.99NS, SIMULATED TRR = 5.79NS.
*
*
* RAD: 5E12
* TYPE: NEUTRON
* TEMP: 27
*
*
.SUBCKT D1N4148/27C/RAD1 99   2
D1   99    2 DFOR
C1    2   99 1.2202E-12
.MODEL DFOR  D          (
+         IS = 1.04734E-8
+         RS = 0.7505
+          N = 1.873917
+         TT = 7.2E-9
+        CJO = 2.34983E-13
+         VJ = 0.4
+          M = 2
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.9
+         BV = 165
+        IBV = 1E-6
+ )
.ENDS
*$
*
* XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* MEASURED TRR = 5.67NS, SIMULATED TRR = 5.61NS.
*
*
* RAD: 2E13
* TYPE: NEUTRON
* TEMP: 27
*
*
.SUBCKT D1N4148/27C/RAD2 99   2
D1   99    2 DFOR
C1    2   99 1.30456E-12
.MODEL DFOR  D          (
+         IS = 6.20257E-9
+         RS = 0.7388511
+          N = 1.805135
+         TT = 7.3E-9
+        CJO = 3.05464E-13
+         VJ = 0.4
+          M = 1.824741
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.8991
+         BV = 163
+        IBV = 5E-6
+ )
.ENDS
*$
*
* MEASURED TRR = 3.4NS, SIMULATED TRR = 1.521NS.
*
* RAD: 2E14
* TYPE: NEUTRON
* TEMP= 27
*
.SUBCKT D1N4148/27C/RAD3 99   2
D1   99    2 DFOR
C1    2   99 1.34841E-12
.MODEL DFOR  D     (
+         IS = 7.51054E-9
+         RS = 1.672287
+          N = 1.864477
+         TT = 1E-9
+        CJO = 1.652E-13
+         VJ = 0.3619
+          M = 1.721
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.85
+         BV = 148
+        IBV = 2E-6
+ )
.ENDS
*$
*
* BV, IBV, XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* MEASURED TRR = 3.379NS, SIMULATED TRR = 3.062NS.
*
* RAD: PRERAD
* TEMP= -55
.MODEL D1N4148/-55C   D      (
+         IS = 1.26351E-8
+         RS = 0.7600063
+          N = 1.953465
+         TT = 2.424E-9
+        CJO = 1.72434E-12
+         VJ = 0.3026211
+          M = 0.2
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.998001
+         BV = 1E5
+        IBV = 1.0E-10
+ )
*$
*
* GENERIC FUNCTIONAL EQUIVALENT = 1N4148
* TYPE: DIODE
* SUBTYPE: SWITCHING
* THIS FILE CONTAINS 1 MODEL THAT CAN BE USED AS A TEMPERATURE TRACKING
* MODEL FROM -55 TO 125 DEG C.
* THIS MODEL CAN BE USED FOR ALL OF THE FOLLOWING DEVICES:
* 1N4148
* 1N4148-1
* 1N4148-1JTXV
* THE ROOM TEMPERATURE PRE-RAD PARAMETER SET SIMULATES NEARLY
* IDENTICALLY TO THE  -55 AND THE 125 DEG C WHEN .TEMP IS USED.  THIS
* PARAMETER SET CAN BE USED  AT ALL TEMPERATURES BETWEEN -55 AND 125 DEG
* C.
* PARAMETER MODELS EXTRACTED FROM MEASURED DATA.
*
* MEASURED TRR = 4.681NS, SIMULATED TRR = 6.544NS.
*
*** CAUTION: THE MEASURED TRR AND THE PSPICE CIRCUIT SIMULATED TRR ARE
* DIFFERENT.  THIS COULD POTENTIALLY LEAD TO ERRORS IN CKT. SIMULATIONS IF
* USED AS A RECTIFIER OR SWITCHING DIODE
*
* BV, IBV, XTI, EG HAVE NOT BEEN EXTRACTED AND ARE SET TO DEFAULT VALUES.
*
* RAD: PRERAD
* TEMP= 27
.MODEL D1N4148/TEMP   D      (
+         IS = 1.27106E-8
+         RS = 0.7546332
+          N = 1.9215823
+         TT = 3.679E-9
+        CJO = 1.72434E-12
+         VJ = 0.3026211
+          M = 0.2
+         EG = 1.11
+        XTI = 3
+         KF = 0
+         AF = 1
+         FC = 0.998001
+         BV = 1E5
+        IBV = 1.0E-10
+ )
*$

555 extract from anl_misc.lib Orcad

.SUBCKT 555C GND TRIGGERbar OUTPUT RESETbar CONTROL THRESHOLD DISCHARGE VCC 
* 
* CMOS 555 TIMER
*
R_R1     CONTROL VCC 150K 
R_R2     2 CONTROL 150K 
R_R3     GND 2 150K 
E_EMIR   VDD GND VCC GND 1
M_M1     DISCHARGE 1 GND GND NCHAN555 L=2U W=1000U
E_EVAL   1 GND 13 GND 1
R_U6_R1  TRIGGERbar 2 1000G 
R_U6_R2  TRIGGERbar 2 1000G 
E_U6_E1CMP  3 GND 2 TRIGGERbar 10K
R_U6_R3  3 23 10MEG 
R_U6_R4  GND 23 10MEG 
D_U6_D2CLMP  23 4 DIODE 
D_U6_D1CLMP  GND 5 DIODE 
V_U6_V2  23 5 dc 0.8V  
E_U6_E1  4 GND POLY(1) VDD GND -0.8 1
R_U7_R1  CONTROL THRESHOLD 1000G 
R_U7_R2  CONTROL THRESHOLD 1000G 
E_U7_E1CMP  6 GND THRESHOLD CONTROL 10K
R_U7_R3  6 21 10MEG 
R_U7_R4  GND 21 10MEG 
D_U7_D2CLMP  21 7 DIODE 
D_U7_D1CLMP  GND 8 DIODE 
V_U7_V2  21 8 dc 0.8V  
E_U7_E1  7 GND POLY(1) VDD GND -0.8 1
M_U2_U1_M4  9 OUTPUT GND GND NCHAN555 L=2U W=1000U
M_U2_U1_M3  9 17 GND GND NCHAN555 L=2U W=1000U
M_U2_U1_M6  10 9 GND GND NCHAN555 L=2U W=300U
M_U2_U1_M8  13 10 GND GND NCHAN555 L=2U W=250U 
M_U2_U1_M1  11 OUTPUT VDD VDD PCHAN555 L=2U W=1000U
M_U2_U1_M2  9 17 11 11 PCHAN555 L=2U W=1000U
M_U2_U1_M5  10 9 VDD VDD PCHAN555 L=2U W=300U
M_U2_U1_M7  13 10 VDD VDD PCHAN555_OUT L=2U W=350U
M_U2_U2_M4  12 18 GND GND NCHAN555 L=2U W=1000U
M_U2_U2_M3  12 13 GND GND NCHAN555 L=2U W=1000U
M_U2_U2_M6  14 12 GND GND NCHAN555 L=2U W=300U
M_U2_U2_M8  OUTPUT 14 GND GND NCHAN555 L=2U W=250U 
M_U2_U2_M1  15 18 VDD VDD PCHAN555 L=2U W=1000U
M_U2_U2_M2  12 13 15 15 PCHAN555 L=2U W=1000U
M_U2_U2_M5  14 12 VDD VDD PCHAN555 L=2U W=300U
M_U2_U2_M7  OUTPUT 14 VDD VDD PCHAN555_OUT L=2U W=350U
M_U2_U3_M1  16 25 VDD VDD PCHAN555 L=2U W=1000U
M_U2_U3_M2  17 24 16 16 PCHAN555 L=2U W=1000U
M_U2_U3_M3  17 24 GND GND NCHAN555 L=2U W=1000U
M_U2_U3_M4  17 25 GND GND NCHAN555 L=2U W=1000U
M_U2_U4_M1  18 20 VDD VDD PCHAN555 L=2U W=2U
M_U2_U4_M2  18 RESETbar VDD VDD PCHAN555 L=2U W=2U
M_U2_U4_M3  18 20 19 19 NCHAN555 L=2U W=1000U
M_U2_U4_M4  19 RESETbar GND GND NCHAN555 L=2U W=1000U
M_U2_U5_M1  20 24 VDD VDD PCHAN555 L=2U W=2U
M_U2_U5_M2  20 21 VDD VDD PCHAN555 L=2U W=2U
M_U2_U5_M3  20 24 22 22 NCHAN555 L=2U W=1000U
M_U2_U5_M4  22 21 GND GND NCHAN555 L=2U W=1000U
M_U2_U6_M2  24 23 GND GND NCHAN555 L=2U W=1000U
M_U2_U6_M3  24 23 VDD VDD PCHAN555 L=2U W=2U
M_U2_U7_M2  25 RESETbar GND GND NCHAN555 L=2U W=1000U
M_U2_U7_M3  25 RESETbar VDD VDD PCHAN555 L=2U W=2U
R_U2_R1  RESETbar GND 250G 
J_J1     VCC GND GND JNEMOD 
R_R6     GND VCC 192K 
*
.MODEL DIODE D RS=0.01
.MODEL PCHAN555 PMOS CGBO=1P CGDO=1P CGSO=1P VTO=-0.2
.MODEL NCHAN555 NMOS CGBO=1P CGDO=1P CGSO=1P VTO=0.2
.MODEL PCHAN555_OUT PMOS CGBO=1P CGDO=1P CGSO=1P VTO=-0.2 CBD=200P
.MODEL JNEMOD NJF VTO=-2.5 BETA=5.12U
.ENDS    555C
*
*|* CMOS 555 TIMER CONNECTED IN ASTABLE OPERATION
*|.LIB MISC.LIB
*|.PARAM CVAL=20N
*|VRST 4 0 PULSE(1 0 700U 1U 1U 400U 1)
*|C2 3 0 10P
*|VCC 8 0 5
*|RA 8 7 4700
*|RB 7 6 2200
*|C1 6 0 {CVAL}
*|X1 0 6 3 4 5 6 7 8 555C
*|CTRL 5 0 10P
*|.IC V(6)=0
*|.TRAN 10U 800U
*|.PROBE
*|.END

*$
* This model is for the old bipolar 555 supplied by National
* Semi Lm555, it is essentially the data schematic entered
* with some manipulation of the bipolar parameters to correct 
* drive capability and timing. The max frequency of 100k as 
* hinted at by Nat Semi is maintained but does conflict with 
* the trigger propagation delay. It would seem that the real part
* is capable of higher freqs. The high current transients with 
* change of output are seen with this model.
.subckt 555b 1 2 3 4 5 6 7 8
  q_q2     18 31 32  qnpn555 
  q_q1     18 6 31  qnpn555 
  q_q4     17 5 30  qnpn555 
  q_q3     17 30 32  qnpn555 
  q_q5d    15 18 8  qpnp555 
  q_q5     18 18 8  qpnp555 
  q_q6d    16 17 8  qpnp555 
  q_q6     17 17 8  qpnp555 
  q_q11    19 9 20  qpnp555 
  q_q9     22 24 19  qpnp555 
  q_q10    1 25 24  qpnp555 
  q_q8     21 23 19  qpnp555 
  q_q7     1 2 23  qpnp555 
  q_q12    21 22 1  qnpn555 
  q_q13    22 22 1  qnpn555 
  r_r1     20 8 1k 
  r_r3     25 5 5k 
  r_r4     1 25 5k 
  q_q16    15 16 1  qnpn555 
  q_q15    16 16 1  qnpn555 
  q_q17    14 15 13  qnpn555 
  q_q18    13 21 1  qnpn555 
  q_q19    12 13 1  qnpn555 
  q_q21    14 14 12  qnpn555 
  r_r5     5 8 5k 
  r_r6     14 9 7.5k 
  r_r8     1 32 10k 
  q_q22    9 9 8  qpnp555 
  q_q22d   10 9 8  qpnp555 
  q_q20    10 12 1  qnpn555 
  r_r10    13 10 4.7k 
  q_q23    11 10 26  qnpn555  .5
  q_q26    3 29 1  qnpn555  .5
  r_r11    27 26 100 
  r_r12    1 26 3.3k 
  r_r14    26 29 120 
  r_r15    11 8 6.2k 
  q_q27    8 11 28  qnpn555 
  q_q28    8 28 3  qnpn555 
  r_r16    3 28 3.9k 
  q_q24    1 11 3  qpnp555 
  q_q25    27 4 14  qpnp555 
  q_q14    7 27 1  qnpn555
  cslow1   15 0 40p
  cslow2   16 0 40p 
  cslow11  21 0 40p
  cslow22  22 0 40p 
.model qnpn555	npn(is=14.34f xti=3 eg=1.11 vaf=74.03 bf=65.62 ne=1.208
+		ise=19.48f ikf=20m xtb=1.5 br=9.715 nc=2 isc=0 ikr=0 rc=1
+		cjc=40p mjc=.3416 vjc=.75 fc=.5 cje=40p mje=.377 vje=.75
+		tr=58.98n tf=1n itf=.6 vtf=1.7 xtf=3 rb=10)
.model qpnp555	pnp(is=650.6e-18 xti=3 eg=1.11 vaf=115.7 bf=70.35 ne=1.829
+		ise=180.5f ikf=20m xtb=1.5 br=4.146 nc=2 isc=0 ikr=0 rc=.715
+		cjc=40p mjc=.5383 vjc=.75 fc=.5 cje=40p mje=.3357 vje=.75
+		tr=119.9n tf=1n itf=.65 vtf=5 xtf=1.7 rb=10)
.ends

*|* BIPOLAR 555 TIMER CONNECTED IN ASTABLE OPERATION
*|.LIB MISC.LIB
*|.PARAM CVAL=20N
*|VRST 4 0 PULSE(1 0 700U 1U 1U 400U 1) 
*|C2 3 0 10P
*|VCC 8 0 5
*|RA 8 7 4700
*|RB 7 6 2200
*|C1 6 0 {CVAL}
*|X1 0 6 3 4 5 6 7 8 555B
*|CTRL 5 0 10P
*|.IC V(6)=0
*|.TRAN 10U 800U
*|.PROBE
*|.END

*$
*End of 555C model

LTSpice 555 model

 Copyright � Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008.  All rights reserved.
*
.subckt NE555 1 2 3 4 5 6 7 8
A1 N001 2 1 1 1 1 N003 1 SCHMITT Vt=0 Vh=1m
R1 N001 1 5K
R2 5 N001 5K
R3 8 5 5K
S1 1 7 N007 1 D
A2 N011 N003 1 1 1 1 N008 1 SRFLOP Trise=100n tripdt=10n
A3 6 5 1 1 1 1 N012 1 SCHMITT Vt=0 Vh=1m
S2 8 3 N009 1 O
S3 3 1 1 N009 O
A6 1 N006 1 N008 1 1 N007 1 OR Ref=.5 Vlow=-1 Trise=100n
R7 8 1 4K
R9 2 1 1G
R10 6 1 1G
A4 1 N008 1 N006 1 N009 1 1 OR ref=.5 Vlow=-1 Trise=100n
A5 4 1 1 1 1 N006 1 1 SCHMITT Vt=.7 Vh=1m
D1 4 1 DR
A7 1 N006 1 N012 1 1 N011 1 OR
D2 8 4 400uA
.model DR D(Ron=150K Roff=1T Vfwd=1.6)
.model O SW(Ron=6 Roff=1Meg Vt=0 Vh=-.8)
.model D SW(Ron=6 Roff=.75G Vt=.5 Vh=-.4)
.model 400uA D(Ron=1K Ilimit=400u epsilon=.5)
.ends NE555

The diodes in your circuit all have reverse polarity compared to your circuit diagram.

For example: netlist

D1 Net-_C2-Pad1_ Net-_D1-Pad2_ D1N4148

Anode comes first and is connected to C2 according to the netlist. This is wrong.

It is a pity that the Eeschema library designers choose to name the cathode as pin 1, contrary to all spices, where anode comes first. So you have to set an alternate node sequence
2 1
to your diodes.

Our select the generic diode from library Simulation_SPICE.

This is what I get with correct diodes:

out

3 Likes

It is a pity that the Eeschema library designers choose to name the cathode as pin 1, contrary to all spices, where anode comes first. So you have to set an alternate node sequence 2 1 to your diodes.

I would rather say it is a pity that the decades-old SPICE convention (pin1=anode) is in conflict with the real-component and IPC convention that pin1=cathode. Both conventions are entrenched and practically impossible to change. Kicad being primarily a layout package, the IPC convention seems to make more sense if you have to pick one.

Periodically it gets suggested that diode symbols in the library get shipped with the alternate node sequence preset so they work for both simulation and layout, but I don’t know if there are drawbacks to that approach.

3 Likes

Great !!
Now it’s working… :slight_smile:

IIRC, it’s just because they followed a different industry standard for footprints, when I mentioned it before. Spice_Node_Sequence="2 1" could easily be added to the official D diode symbol… Maybe they would listen to you?

1 Like

It’s not so simple. Changing such a thing will break all the existing schematics in which that diode is used. This is a result of the way KiCad V5.1.x and earlier works because schematic symbols are linked directly from the libraries.

In KiCad V6 schematic symbols are only updated from the data from the libraries then you order KiCad to do so.

Why would it break all? Spice_Node_Sequence only affects simulations and no PCBs, and I would guess most who don’t want to have a wrong simulation schematic have replaced Device:D with pspice:DIODE or Simulation_SPICE:DIODE, which are not compatible with PCBs, (or my Elektuur:D or Generic:D for that matter, that are) after being bitten… I think Spice_Node_Sequence defined in the schematic is not overwritten by Spice_Node_Sequence defined in the symbol?

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In LTspice you have not defined what type of diode you are using. It just says ‘D’. Please right click on ‘D’ and choose a diode, i.e. 1N4148. If not, you are using “the defaults” and the result can vary very much in result.

Maybe not so much of a difference in result with this particular netlist. But if you place a NMOS in LTspice and do not choose what transistor model you will be using the result of the simulation will most likely differ very much from real world. (A Vt of 1V or 6V is a huge difference if you drive the gate directly from the uC.)