Hello,
I am trying to build up a library of spice models for common 74xx series and related logic chips. In my specific case I am building a symbol library which contain all pins in a single symbol, including Vcc and Gnd.
Since manufacture spice models seem to usually only include a single unit, I have built my own wrapper library which contains subckts of the entire chip. This seems to work in some cases. For example:
MyLibrary.lib
*****************************************************************************
*
* 74xx Series Full Models
*
*****************************************************************************
*
* Components using Manufacture Models
*
*****************************************************************************
.SUBCKT 74HC04 1A 1Y 2A 2Y 3A 3Y GND 4Y 4A 5Y 5A 6Y 6A VCC
.INCLUDE elements/SN74HCS04.cir
XU1A 1Y 1A VCC GND SN74HCS04
XU1B 2Y 2A VCC GND SN74HCS04
XU1C 3Y 3A VCC GND SN74HCS04
XU1D 4Y 4A VCC GND SN74HCS04
XU1E 5Y 5A VCC GND SN74HCS04
XU1F 6Y 6A VCC GND SN74HCS04
.ENDS 74HC04
This 74HC04 includes the manufacture spice model from the file elements/SN74HCS04.cir and then instantiates 6 units, mapping them correctly to the overall chip package pin out. All good so far.
However, in some cases this does not seem to work.
I also have the manufacture spice model for the TLC555 timer. In that case I do not need multiple units, I simply want to rearrange the pin order. I know I can do pin mapping inside KiCad, but in order to provide a unifed library experience, I want to wrap the manufacture model in my own subckt with the argument order rearranged. Seems like it should be simple. Here is my attempt.
MyLibrary.lib
.SUBCKT MYTIMER GND TRIG OUT RESET CONT THRES DISC VCC
.INCLUDE elements/TLC555.cir
XU1A THRES CONT TRIG RESET OUT DISC VCC GND TLC555
.ENDS MYTIMER
This does not work. I get the following error when trying to run the simulation.
Run Simulation Output
Note: Compatibility modes selected: ps lt a
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Warning: Nesting of subcircuits with parameters is only marginally supported!
Circuit: KiCad schematic
Error on line:
m.xu3.m.xu1a.xmn17.m1 probe_int_net-_u3-disch__xu3_7 xu3.xu1a.gout 0 0 xu3.xu1a.xmn17.tlc55x_nmosd_hv xu3.xu1a.xmn17.w= xu3.xu1a.xmn17. 3.500000000000000e-04 l= 9.999999999999999e-06 m= 2.000000000000000e+01 ad= 3.500000000000000e-10 as= 3.500000000000000e-10 pd= 3.520000000000000e-04 ps= 3.520000000000000e-04 nrd= 2.857142857142857e-03 nrs= 2.857142857142857e-03
could not find a valid modelname
Error: circuit not parsed.
I should mention, if I use the manufacture spice model directly (elements/TLC555.cir) instead of my wrapper from my library, it works perfectly.
Furthermore, if I move the .INCLUDE elements/TLC555.cir outside the subckt, then it also works, but then my library is polluted at the top-level with internal circuits from each sub module, ruining my library interface within KiCad when selecting the model from the library.
Why does this error occur?
Why does it not occur for the other device (the 74HC04)?
Is there any way to fix it without polluting the top level?
I am happy to provide any further details.
Thank you kindly,
The Moon Cactus