I was wondering if it is possible to create a NetTie via? That is, use a via or padstack to connect two different nets. I am thinking of something like the through hole NetTie but the two pads are coincident instead of separated.
I can almost made it work but for some reason the top layer does not connect properly. The images below show each layer with the other layers turned off. (4 layers). The GND and GNDP nets are connected with the NetTie in the schematic. The top layer and In1 zones are GND. In2 and the bottom layer zones are GNDP.
KiCad does not support using a single pad (or a via) as a net tie. A net tie footprint must always have two or more pads. So, it is not possible to define a single drilled pad / via where some layers connect to one net and some layers connect to a different net. You have to instead use a copper connection on one of the outer layers to connect multiple pads together. Those multiple pads can be SMD or through-hole, but each pad will connect to a single net.
Yes, the NetTie Via I created (see “NetTie Via.kicad_mod” attached in the first post) has two through hole pads. They are coincident. So, the copper connecting the two pads is the plated through hole.
I have determined why the first case appears to not connect. It.is related to some custom rules I use to handle DRC errors when you use a NetTie. I have found that if I use a larger pad diameter I can get the proper connection. I have not found the exact rule but I think it must be a clearance to hole rule.
Abusing a via as a net tie does not seem very sensible to me. To me it makes more sense to use a THT pad as a net tie. Such a net tie could have some copper layers disabled, and then put an SMT pad on those copper layers. A net tie already has a schematic symbol and a footprint.
(Currently there is no GUI option to put an SMT pad on an inner layer, but if you hack into the file, to put it on an inner layer, the pad tends to stay there and work normally. I believe there already is a gitlab issue for pads on inner layers.)
I am considering doing that and wanted to understand what the limitations were so that I why I started looking further into it. The KiCad feature that piqued my curiosity is the new pad stacks. I think this “NetTie Via” takes advantage of them.
It might be the case that we do not have to make any changes. I’ve found a way I think works. I’ve attached a sample schematic and layout that demonstrates the feasibility. I would not characterize this as an exhaustive test and it is a bit quirky to use (you have to remember there are two coincident pads) but it does seem to work.
The minimum pad size caveat I mention below may require a feature request to eliminate this constraint.
Yes. The demo I attached demonstrates this. It consists of two THT pads that are overlapped and the copper layers are defined as “Connected layers only”.
There is one caveat. The minimum size of the THT pad used in the NetTie Via is the hole diameter plus the hole clearance. Otherwise, when you use a zone connection the zone does not intersect the pad. So, for a nominal 0.3mm hole and a hole clearance of 0.25mm you require a pad size of at least 0.8mm. In the example I used a diameter of 1.0mm. If you make the hole smaller and/or reduce the hole clearance you can reduce the size of the pad.
This was the constraint that prevented the connection in the first post. The pad on the top layer was 0.6mm.
I’m still on KiCad V8 and can’t see your project right now. Having two THT pads at the same location is not optimal. It will also have two drilled holes at that location, and PCB manufacturers may reject your PCB for that. A combination of a single THT pad and SMT pads does not have this issue, but it also does not automatically create pads on only the used layers. This can be optimized further, and an improvement suggestion may be worth a feature request on gitlab.
I used a single through hole pad and a single SMD pad. I edited the THT pad so it only appears on F.Cu. I edited the SMD pad layers to In1.Cu, In2.Cu and B.Cu. I also changed remove_unused_layers to “no”. If you open the file in an editor you get a better idea of what the details are.
In the project file there is a custom rule:
(rule "NetTie copper to hole"
(condition "A.memberOfFootprint('NT*') && B.Type == 'Zone'")
# override hole and zone clearance
# The result is either the hole size + hole clearance or
# the hole size + clearance whichever is larger.
(constraint clearance (min 0.2mm))
(constraint hole_clearance (min 0.2mm))
)
It would have been slightly easier if you turned that around. Connect the inner layers to the THT pad, ( with it’s automatic only draw the pad on connected layers) and keep the SMT pad on the outside). But also nice to see that hacking an SMT pad onto an internal layer still works.
