Netlist trouble (and some other stuff)


Split thread as deviation from original topic was blatant.

Schematic Border and Title Block

In many cases that is actually an effective way to learn. You would be surprised by how much engineering happens in the hour or so after somebody says, “Hey! Look at what happens when I do {something}. I never noticed anything like that before.”. Of course, it helps if the {something} has at least a small amount of reasoning behind it, not just a random action.

On this Forum, and many similar independent user Forums, “initiative” is an admirable quality. The most welcome posts, and usually the ones receiving the greatest attention, are written similar to, “Well, I need some help with {some feature, process or task}. Here is what I have already tried: { . . . . } and the results I received were { . . . . }. How can I achieve results that are closer to my objectives?”



Why should I read the manual if I can ask the forum?


More like …

Why should the rest of us waste our time helping those who can’t be bothered to help themselves.


I agree 100%. Actually, when I had got stuck in my C-programming, of the AtMega8 chip, there was no such “forum” (nor still is), to give a precise solution. So I had resorted to “Hit & Trial” method there. [ I installed two 2P4W switches on both sides of the programming cable, one on the computer output side, the other at the programmer side, so that I could quickly cut-off both ends by just sliding the two switches. Thus, I did not have to remove & insert my USB cable every time. So, this way. I was quickly able to try 100-different C-code variations per day, till I came across the one that worked.]. Yes, “Hit & Trial” was the only way I got it right.

But here in KiCad, I got the precise answer to my problem faster, than I could do one Hit & Trial with that elaborate circuit, where to generate one Net-List takes 3 to 5 minutes each time. This longer time may be because I still have not put the library in my local E: drive. My “cvpcb” has now stopped hanging, but still takes that long time on each run. Is that normal?


However, if you have found a way yourself, by your own 'hit & trial" method, I am sure you won’t be able to keep it to yourself. (Even when you know, that the solution is written there, in the very first line of the help menu)[quote=“pedro, post:30, topic:2430”]
Why should I read the manual if I can ask the forum?

Why I address the veterans as “Sir” ? Because, I respect their ability to interpret the “manual” & produce the practical results into the projects. Not everyone can do that,…else we would not have teachers in KiCad with over fifty thousand viewers, even on YouTube.


No one has said they wouldn’t help you, in fact you have received help. But there would likely be even more people willing to help you if you said something like …

“I’ve tried this and I’ve tried that but can’t figure it out, can any one help me out?”

instead of


No, shouldn’t take that long. I find generating a netlist takes 1-2 seconds.


Right Sir,
that is proper way to put it. Sorry for the bad language used instead. However, due to the “cvpcb” long time taking problem in this case, I could not try it out at my end first. Thanks, for assuring your help always.


So Sir,
Do I need to go into those 20 steps, to put the library into my local E: drive? - As given earlier by you in the blog of “cvpcb” hanging problem?


I don’t think having local footprint libraries will help with generating the netlist, that must be a different problem. Is your project stored on a network drive?


I’d ask you to create a new topic if you start to address a different topic than what the original thread was about and you didn’t start it (=i.e. it’s not yours).
If this had been your thread, I would have left it alone.


My project is not stored on a network drive. If you tell me how to do it, I will put it there.

@Joan_Sparky Thanks for putting it in a new heading. Yes the matter went off the original topic.


No, I am not suggesting that, I was trying to find why your netlist generation is so slow. Perhaps you just have a huge schematic and a very slow computer.


But even a small schematic, also takes about 3 minutes to load the net-list. (just a 555 timer, multivibrator, with a pcb relay, to put a pump on for 2 minutes and off for 3 minutes).
The schematic PDF file is up-loaded below:-
coolerTimer-1.pdf (19.7 KB)

The slow speed could be due to a slow net? My computer seems to be fast enough with windows 8.

I have not come to the big schematic yet, which I plan to load, in 3-parts, one by one, or else the pcb board will be too congested to spread the layout properly. That means for each additional part, I will have to generate the net-list again. So I wonder what time will that big board take?


You need to get your libraries local anyway, if you are permitted to do so by the PC owner.
Otherwise Murphy will bite you with an ISP hiccup at some critical point.

Your schematic needs some work.
Avoid wires running across symbols as as happened with the 555.
Try to connect only 3 wire segment at a junction (555 pin 6)
Avoid joining multiple wires at a symbol pin eg C2, D4 and the 555 pin 1 & 8, they may not be connected as there is no junction showing.


Thanks a lot Sir, that hint given today, was crucial.,:relaxed:

After I followed the 22 steps in this page below:-
kicad-doc - KiCad new documentation format repository)

& after I downloaded the footprint libraries in my local E: drive,…
now my “cvpcb” takes only 2 seconds to load the net-list in the same schematic.
Also, I tried in the bigger schematic, & it took only 6 seconds…!!!..WoW…!!!

Since I started using KiCad, this problem had plagued me, - the net-list always took 3 to 5 minutes to load, and at times it took so long that I had to shut down KiCad.
Today is the FIRST time, that the “net-list” was generated in less than 10 seconds…!!

@bobc -thanks for posting these 22-steps…problem solved…!!.. :grin:


Hm, I think @SchrodingersGat should have enough support for changing the Github hook with such usability issues caused by the current status-quo.