Though it is a pain, there is a setting for any element to be shown only on the first page. Select the element in the layout editor, then there’s a box that lets you choose if it’s on the first page only, everywhere but the first page, or everywhere. You can achieve stuff like this.
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How can I increase the size of the schematic page borders? (My schematic is kind of big)
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Or, If some parts of my schematic go outside the page borders, will the net-list still generate? & will the Pcbnew still respond normally? (as some components are outside the border in the schematic due to lack of space inside the border?)
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Does the net-list (& then the Pcbnew), recognize components of the schematic drawn outside the borders?
Please explain & help. Why should I waste time in “hit & trial” methods?
- File-> Page Settings, set paper size as desired, or set to user and define your own size.
2 & 3 The drawing frame is cosmetic and has no impact on the netlist. The same applies to eeschema and pcbnew.
Thanks Sir,
I think you mean: that even if I continue drawing the schematic outside the “cosmetic” border, the net-list will still generate, (& that,…I also can increase the schematic paper size if I want to, - to make it look neat?) - but that is optional? Have I got it correct?
Yes, that’s correct. You can even turn off the border completely if you want.
blank.kicad_wks (382 Bytes)
Hi, I am using the latest stable version of KiCad under Windows 7 64 bit. I have quite a large schematic that for readability I want to print at A2. The format of the drawing is A2. Printing to A3 is fine, even though the print previews is cut off top and bottom. (Konica Minolta C554 that downscales in its own software). If I print A2 (HP Design Jet 800 42) the print is exactly the same as the print preview.
If I go to the page layout editor, the print looks fine, the preview is fine, and the A2 print is fine with all borders present.
Is this a bug in the schematic software, or in the Page layout / setup software?
I have tried custom settings, translating the A2 size to imperial units (16.53" x 23.38") and the top / bottom borders are still missing in print preview of the schematic.
Setting the page to A1 loses all except some of the bottom border in schematic preview. It looks OK in the page layout editor, but page editor print preview shows no bottom or right border even at 20% zoom.
I did not try A0!
Any ideas?
Is what a bug? I can’t see where you have a problem.
Also, please start a new thread instead of resurrecting an old one.
Thanks bobc . It seemed a simialr theme, but I will start a new thread
I tried the blank worksheet posted above by @bobc with a recent 5.0 nightly. It does indeed get rid of the border around my layout in PCBNew (but not the title block) but after saving, closing and re-opening the file in PCBNew, the border is back again and the worksheet selection in the Page Settings dialog is blank. A bug, or am I doing something wrong? Does the worksheet file need to be in a special location?
EDIT: Never mind - I see that you can turn off the worksheet and border visibility entirely, from the “Items” (fka “Render”) palette - awesome! Leaving this here in case it helps someone else.
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I am trying to create my own title block. I have some experience with KiCad (8 moderately complex 4-layer boards to date) and I have read the previous posts, but I’m still stumped. I think that I am running KiCad 5.0.1 (that is what I downloaded from the KiCad download site, but the heading on my KiCad program manager window says KiCad (2017-12-26 revision 90818af)-master; is this version 5.0.1 or not?). I am using a Mac running OS X version 10.12.6 Sierra.
I opened Worksheet Layout Editor (in the Program Manager it called it pl_editor; is this what I want?) whereupon I got a window containing a border and a title block.
I need to define my own title block because the one that comes up is badly organized and is missing some fields that I need. I would like to erase the current one and start again, however I cannot see how to do that. My questions:
- How do I erase the current title block?
- The left sidebar contains a lot of line and Text entries like test2: Text and segm5: Line. There is no description of where they are, what they are or how I use them. How do I draw a title block and enter the requisite fields? Better yet, how do I create a template for a title block to use in all my schematics?
- How do I specify fields, with contents, font sizes and thicknesses and fixed text.?
Thanks in advance.
Best regards,
Peter
2017? No, I don’t think this is the latest.
This is the correct tool, but it is a bit cryptic. You should really refer to the online manual. Here is the direct link to the English version of the manual in HTML format. Check here for other languages and formats (it is available as HTML, PDF and ePub).
A bit of a warning, though. KiCad v5 (you have taken hermit’s advice and updated to v5.0.1, right?) is recently released. The documentation always lags and may not have been updated fully. So, if you find an error in the documentation it may be either a true error, or it may be older not-up-to-date information. The place to report errors in the documentation is here. Please feel free to ask here for clarifications or to make sure an issue you have with the documentation is not PEBKAC. Granted with documentation, many PEBKAC issues that aren’t solved with RTFM can be resolved with clarifications to the documentation. 
Almost forgot to mention. Your edits in the pl editor will be saved to a .kicad_wks file that you will then need to point to in the Page Settings of your schematic and/or pcb.
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The worksheet editor has not really been touched between v4 and v5. So the documentation should be up to date.
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You have a pre v5.0.0 Nightly build, a long way back too
Thanks All. I have downloaded and installed 5.0.1 properly this time (finger trouble last time…). SembazuruCDE, your help is greatly appreciated.
Thanks again to all who responded.
Best regaards,
Peter
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On Friday I have installed 5.0.1 (Windows 64bit). I moved the only one my design I have done with KiCad (4.0.7) to it. And I found that Title Block definition that worked well in 4.0.7 now gives me error picture in PcbNew (in schematic it is OK).
Here is how it looks in schematic:
And here how it looks in PcbNev:
It is not a problem during updating the 4.0.7 project to 5.0.1. I have tried to add my mm.kicad_wks to default kicad.pro design and got the same result.
Is the logo imported to the worksheet file as a bitmap, or did you convert the bitmap to a poly-polygon using Bitmap2component as described in section 10.4 of the pl editor manual?
I ask because I have a logo on my worksheet file (done long ago, so I don’t recall my exact steps) that is a poly-polygon and I don’t see the issues you showed (negative and scaled wrong in pcbnew). I haven’t tried the adding bitmaps to the worksheet so I don’t know if I would have the same issue or not.
Yes.
I had to check it as I don’t remember how I have done it. I used that frame editor only once and long time ago (March 2018), and supposed that work done once is forever. I even didn’t remembered that there are more than one possibility to insert graphic into it so writeing my post I was sure that it has to work that way for all logos.
Interesting lines of file:
(bitmap (name bm1:Bitmap) (pos 95 14) (scale 0.5)
(pngdata
(data "89 50 4E 47 0D 0A 1A …
So it looks that PcbNew ignores scale. But where the positive/negative information is located?
In 4.0.7 it had to work well, as if not I would certainly noticed it. But now when I installed 5.0.1 I don’t wont to reinstall 4.0.7 just to check it.
I will report a bug.
I have done it. But may be it is not an error but just kicad_wks format was changed and my file need be updated. Who knows…
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