in this screenshot you can see the schematic and the corresponding pcb. Problem: The net ADC_CLK (blue) should be only connected to IC601(blue) but not to IC602(green). Pin 3 of IC602 should be ~ADC_CS which is not the case on the pcb.
The issue was raised https://bugs.launchpad.net/kicad/+bug/911002, but marked as Invalid for no explained reason. That is really poor practice, at least give a one line reason to make it look different to when the cat walks on the keyboard! It just looks like someone took against it so they unilaterally killed it
I could change the status, but I can’t make it a wishlist item.
There was also some discussion on the dev list https://lists.launchpad.net/kicad-developers/msg20134.html, and although some concerns were expressed, no one seemed dead against it. As usual with many proposed enhancements, it would need an amenable developer to “sponsor” the idea and propose a patch to the dev team.
Connecting 2 hierarchical labels from one sheet to another already fulfills your warning threshold.
In that case it’s actually 4 hierarchical labels labeling 1 net. If you would have local labels in those sheets as well (not to mention pin names) it get’s ugly pretty fast…
Errors like the one you produced are IMHO better catch-ed visually via net highlighting and a more powerful canvas driver.
Both of these are being worked on afaik, with nightlies already being able to highlight nets in EEschema.
I think that would be the problem, it would trigger so many times for normal use cases everyone would just turn it off. It is obvious to a human looking at the schematic “in this case, it’s ok”, but really hard for software, because it has no idea what you are trying to do.
I think Eagle asks whenever you join two nets, if that is intended.
To stop this accidental shorting of nets (done it myself too at least twice), hierarchical pins should either only allow wires to join perpendicular to the pin or have a non-zero length external pin with the usual “x” on the end