Netlist problem. Not a Bug


#1

Hi,

in this screenshot you can see the schematic and the corresponding pcb. Problem: The net ADC_CLK (blue) should be only connected to IC601(blue) but not to IC602(green). Pin 3 of IC602 should be ~ADC_CS which is not the case on the pcb.

Have you experienced this once? Is there a workaround?

Unfortunately this makes me worry to loose confidence in kicad, especially because this is a stable release.

Application: kicad
Version: 4.0.6-e0-6349~53~ubuntu16.04.1 release build
wxWidgets: Version 3.0.2 (debug,wchar_t,compiler with C++ ABI 1009,GCC 5.4.0,wx containers,compatible with 2.8)
Platform: Linux 4.4.0-66-generic x86_64, 64 bit, Little endian, wxGTK
Boost version: 1.58.0
Curl version: libcurl/7.47.0 OpenSSL/1.0.2g zlib/1.2.8 libidn/1.32 librtmp/2.3
USE_WX_GRAPHICS_CONTEXT=OFF
USE_WX_OVERLAY=OFF
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_WXPYTHON=ON
USE_FP_LIB_TABLE=HARD_CODED_ON
BUILD_GITHUB_PLUGIN=ON


#2

Somewhere you have ADC_CLK connected to ~ADC_CS. In the case where a net has two or more labels, KiCad picks one.
The error is somewhere else on the schematic which you have not shown us.

Actually another possibility is that the PCB has tracks with the wrong net labels, this can happen if you move a footprint onto an existing track.


#3

If I use Ctrl+F for ADC_CLK and ~ADC_CS I can’t find any unwanted interconnections. They are all connected with the pins I want.

On the PCB there are no tracks yet.


#4

The evidence tells you the opposite.

If you are so sure you are right, why do you bother asking?


#5

Have you updated the netlist?
(In other words are you sure the schematic and pcb are in sync)

Do you have any hidden power input pins that could connect to these two nets. (Hidden power input pins are global labels.)

Have you run erc? Did it complain for anything?

If nothing else helps: can you share your schematic?


#6

For the ERC everything is fine.

Netlist was updated


#7

I think i would also need the cache lib (or the symbol libs you used)


#8

Hope you can open it now.
windrad.sch is the top file


#9

Found the problem. You have a connection in the main sheet:



#10

great! thank you very much!

would expect that the the ERC would give me a warning here. Is there a way to turn those warnings on?


#11

What warning would you expect to see?


#12

Connecting two input pins is done quite often. If ERC would warn you about that you would ask us how to turn it off.


#13

well, the ERC should warn me that two names label the same net.


#14

Well the erc in future versions will be a bit more powerful. (At least if everything gets implemented that is on the roadmap for v6)
Currently erc only checks pins.


#15

The issue was raised https://bugs.launchpad.net/kicad/+bug/911002, but marked as Invalid for no explained reason. That is really poor practice, at least give a one line reason to make it look different to when the cat walks on the keyboard! It just looks like someone took against it so they unilaterally killed it :frowning:

I could change the status, but I can’t make it a wishlist item.

There was also some discussion on the dev list https://lists.launchpad.net/kicad-developers/msg20134.html, and although some concerns were expressed, no one seemed dead against it. As usual with many proposed enhancements, it would need an amenable developer to “sponsor” the idea and propose a patch to the dev team.


#16

Connecting 2 hierarchical labels from one sheet to another already fulfills your warning threshold.
In that case it’s actually 4 hierarchical labels labeling 1 net. If you would have local labels in those sheets as well (not to mention pin names) it get’s ugly pretty fast…

Errors like the one you produced are IMHO better catch-ed visually via net highlighting and a more powerful canvas driver.
Both of these are being worked on afaik, with nightlies already being able to highlight nets in EEschema.


#17

Joining pins/ports happens. What should not be allowed is wires overlapping the hierarchical sheet box outline, as has happened here


#18

Connecting two pins on a hierarchical sheet from the higher-level (instantiating) sheet is not uncommon. For example, say I have a sheet with some I2C device on it. The device has pins to set part of the I2C address, so I connect those pins to hierarchical labels so I can set the I2C address in the instantiating sheet. I want to use that same sheet a couple of times. On instance 0 I will ground A1 and A0. On instance 1 I connect A0 to VCC and ground A1.

Should the ERC warn me that inputs A1 and A0 on instance 0 are connected together? Of course not.


#19

I think that would be the problem, it would trigger so many times for normal use cases everyone would just turn it off. It is obvious to a human looking at the schematic “in this case, it’s ok”, but really hard for software, because it has no idea what you are trying to do.

I think Eagle asks whenever you join two nets, if that is intended.


#20

Just think about it. If software could easily do this task would there be a need for humans anymore? I hope nobody finds a way to teach this skill to a computer. Otherwise my education is worthless.