Netclasses to be variable clearance depending on context

[mxlemming]

Hi,

I feel like there must be a way to achieve this:
I have an inverter stage - it has 400V, ground and a switch node. The stage uses paralelled MOS that have gate drivers on another board. Standard stuff.

The tricky thing is getting clearances sorted:
I want 2mm clearances between say GND and switch node, and GND and HV,

I would like to keep gate:ground for the low side gate at 0.2mm and gate:switch node for the high side gate, BUT the high side gate must be 2mm clearance from the HV and GND, and the low side gate must be 2mm from the switch node!

Is there some kind of “grouping” functionality I am missing? like I could make a group called “Phase_A_node” and assign that within that group the clearance is 0.2mm but the group as a whole has 2mm.

Apologies if I am missing something well known/obvious. This feels like it must be a problem encountered by every high voltage designer.

[paulvdh]

Net classes are fairly simple. They define a minimum clearance (and track width) between a net, and “the rest of the world”.

For more complex things you can use custom rules. I’ve collected some examples in the thread below.

Custom Design rules Examples

Creating a big clearance between net classes in a “High voltage” section and the rest of the PCB The trick here is to create netclass names starting with a recognizable string (“HV”) and using that in the rules. Rules are also applied in order, and the thread discusses some of the consequences of that. (version 1) (rule "LoW cLeArAnce BeTWeen neTS of THe SAme HV potential" (constraint clearance (min 0.2mm)) (condition " A.NetClass == B.NetClass && A.NetClass == 'HV*' " )) (rule "HIgH cLeA…

[mxlemming]

That was a fast response Paul!

For further context, for anyone looking in future, here is a very early very incomplete snapshot of my problem.

With phase node given clearance - the gate traces are now in violation and there is much wasted copper plane and unconnected pins on the MOSFET…
(can’t post more images because I am new here…)
With phase node at 0.2mm clearance - the low side gate traces are then in violation.

I’ll look into custom rules. Thanks

[paulvdh]

You can also use custom rules in combination with a rule area to constrain them to the location of the that area. There is an example for this in the Syntax Help in the dialog where you create the rules.

[mxlemming]

With the hint and example on the linked page above, I was quickly able to make it generate this automatically, after creating netclasses for each of the phases and the HV bus.

No end of tidying up and finishing the design to do but the major netclass clearance problem appears solved, thanks!