Net-Tie drc errors

[teletypeguy]

I don’t quite understand why I get net-tie drc errors, and I just ignore them, but would be nice to know why. AFAIK, to make a part a net-tie, the pad numbers just get added to the net-tie section in the footprint editor, just like the kicad-provided net-ties. Note: I am still on 7.0.10, so perhaps this is different in the current 8.x version.

Anyway, here is a comparison of a few net-ties:

net-tie-test.zip (16.5 KB)

• three- and two-hole PTH thu designs of mine with overlapping pads
  (these tie ALL inner layers for plane bonding)

• a PTH thru design (2x100mil pads) with only a shorting segment on the bottom,
  and an smt design (0603) with only a shorting segment on the top
  (these are for normally-shorted use, but can xacto cut top or bot trace to open)

• a kicad lib thruhole net-tie (shorts top and bot layers, but not inner, so no use to me)

• a kicad lib smt net-tie (shorts top only, so limited use to me)

And ALL of them throw DRC errors. Maybe I am missing something.

Any comments on refinement, or preventing drc errs?

Application: KiCad x64 on x64

Version: 7.0.10, release build

Libraries:
wxWidgets 3.2.4
FreeType 2.12.1
HarfBuzz 8.2.1
FontConfig 2.14.2
libcurl/8.4.0-DEV Schannel zlib/1.3

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:
Date: Dec 28 2023 21:18:15
wxWidgets: 3.2.4 (wchar_t,wx containers)
Boost: 1.83.0
OCC: 7.7.1
Curl: 8.4.0-DEV
ngspice: 41
Compiler: Visual C++ 1936 without C++ ABI

Build settings:
KICAD_SPICE=ON

[paulvdh]

@teletypeguy

And ALL of them throw DRC errors. Maybe I am missing something.

I am missing the actual DRC violations of your board.

I only have KiCad V8, and after dismissing the DRC violations for missing libriaries, there are only two warnings for text size (meh) and two violations for: **Hole clearance violation (board setup constraints hole clearance 0,25mm; actual 0.0000mm) The text size would be easy to fix.

After a bit of experimentation, I think I understand the DRC violation. This hole clearance is probably calculated between the side of the hole, and the copper of the pad next to it, and this calculation disregards that those pads are part of the same net tie and the overlap is thus intentional. This can be interpreted as a bug to be reported on gitlab.

Your intention appears to be to create a net tie that connects the pads both on the inner and on the outer layers. You can probably move graphic items on a copper layer to inner layers, but this is messy, and doing this with THT pads as you already did is probably the best option.

I modified your JP2 footprint in the footprint editor. I moved the pads a bit further from each other, and then also added an offset for the hole for both of the pads:

After putting that footprint back on the PCB the DRC violation for the hole clearance had disappeared, but I got a DRC violation for incomplete thermal vias. In the PCB Editor, I edited the pad properties (for both pads) and on the connections tab, I changed the Pad Connection from Thermal Relief to Solid, and that fixed that DRC violation too.

This can also be set directly in the footprint in the footprint editor.

The only remaining issue I can see are the tiny retractions in both the zones for the clearance of the “other pad”.

[teletypeguy]

In another thread,
https://forum.kicad.info/t/how-to-connect-power-and-signal-grounds-on-inner-layers/52407/12
@gschelotto discussed manually editing a net-tie footprint. So I tried a mod of an smd net-tie from the kicad library and added a copy of the top-layer poly on In1, In2, and B layers, and set the smd pads to *.Cu for all layers:

JP_NetTie-2_SMD_Pad2.0mm.kicad_mod (1.6 KB)

So that is really nice for full plane bonding!

Still throws DRC errs though:

[teletypeguy]

@paulvdh

After a bit of experimentation, I think I understand the DRC violation. This hole clearance is probably calculated between the side of the hole, and the copper of the pad next to it, and this calculation disregards that those pads are part of the same net tie and the overlap is thus intentional. This can be interpreted as a bug to be reported on gitlab.

Your intention appears to be to create a net tie that connects the pads both on the inner and on the outer layers. You can probably move graphic items on a copper layer to inner layers, but this is messy, and doing this with THT pads as you already did is probably the best option.

Yeah, thanks Paul – it does make sense that it didn’t like my overlapping pads. It sounds like the DRC errors will be different in V8 (and I’m not quite ready to switch), so I will not be concerned about the DRC errs just now.

I am quite happy to find the manual net-tie edit (see above post) as that now allows a proper multi-layer net-tie to be made for either smd or thru-hole pads with a shorting copper polygon (so no overlapping pads needed). This approach will let me build any net-ties I need

One question for any kicad_mod file gurus: is there a notation for “all-inner” that can be used in this edit? The net-tie that I modified is 4-layer, but would need changing for 6-layer…

[teletypeguy]

@paulvdh

I modified your JP2 footprint in the footprint editor. I moved the pads a bit further from each other, and then also added an offset for the hole for both of the pads:

I appreciate you tweaking the footprint and optimizing it. I am going to close this and worry about the drc errs when I get to v8 (shortly).