Hi. I have designed a 4-layer implementation of an Analog Devices LT8711 Zeta Converter.
I have the gerbers for an evaluation board. The designer has connected the signal and power grounds on the top layer and bottom layers and also on an internal layer. The connections are at the top of the 20-pin TSSOP footprint in this picture
I created a fat Net-tie footprint for the top layer but I can’t find any way of replicating that on an inner layer.
Any suggestions please?
I have used net-tie only once to make RFID antenna (shorts with copper its both ends).
I think tere is no way to define net-tie at inner layers, but it should be possible to define THT net tie for all your THT pads under the IC. May be such one net-tie will solve your problem.
But as the signal and power grounds are probably separated in area you just can make them both being the same net (so no net tie problem to be solved) and define their shape separately with overwrite one over another under IC. It can also be one GND zone with right shape.
My example of similar connection:
Green is In1, Blue is bottom. Both zones are GND.
I hid top so that it does not cover the details.
Thanks Piotr. I think that’s how the original designed might have done it.
I’ll stick with the separate grounds. The 2 grounds are joined on the other layers by the thermal vias under the TSSOP-20 package anyway.
Regards, Dave.
KiCad still has a limitation to place footprints only on the front and back layers, and net ties are implemented as footprints (with pads, so you can connect to them). I once saw a hack in which the PCB file was edited in a text editor to place footprints on an internal layer, and apparently this works and you can then move the footprint in KiCad and it stays on that layer.
But I have some doubts about the usefulness of all this. As far as I know this design method is mostly a stubborn artifact from days gone by. As far as I know, more GND is almost always more betterer. And then combine it with physical distance between “noisy” parts (SMPS) and “sensitive” sections (ADC frontend). All ripple current with frequency content higher then a few kHz will always follow the path of least impedance, and not the path of least DC resistance. If at all possible, the currents in a continuous GND plane will always be directly under the track, because this is the smallest loop inductance, and thus lowest impedance. If you make slots in your GND plane, then you force the GND currents around those slots. Thus higher impedance, and you generate more noise, and you hope to mitigate the effects of this higher noise by using more slots in your GND plane. It’s yucky.
Thanks Paul. I’ll have to do more research.
When reading books reviews, it’s common to have non-sensical one-liners describing the “mood” of a book.
I did a short peek for something similar after this search: split GND plane at DuckDuckGo
The references I looked at (not read the whole article) from the first page of that search result:
Separating analog and digital ground planes is a contentious design practice that can create power integrity and signal integrity problems.
Tips and Tricks for Separating Analog and Digital Ground Planes
To make things easier, we can readily debunk all of the foregoing and say they are not true. But, perhaps one of the most important takeaways is that you should NEVER, EVER split ground planes. If you do, you will destroy the integrity of your PDS.
Splitting Planes—The Good, The Bad And The Ugly | PCB Design Blog | Altium
The risk of causing signal integrity, power integrity, and EMI problems with a split in the ground plane strongly outweighs the potential benefit;
The Case for Split Ground Planes | Signal Integrity Journal
At the end of the day, the best mixed-signal PCB design guideline I can give is to use a solid ground plane without any cutouts or gaps.
Should You Split Ground Planes in Mixed-Signal PCB Design? | NWES Blog
I keep the planes as continuous as possible and almost never use slots - they are bad for a few reasons which I will describe
layout - Single ground plane vs split planes? - Electrical Engineering Stack Exchange
Thanks. A great reading list for tomorrow!
I just had a bright moment. These days 4-layer PCB’s are common, and assigning one or both inner layers to GND (Prepreg is much thinner then the PCB core, and thus better coupling and less noise) is much easier then the old days, when most designs were on two layer PCB’s. If you only have two layers, then there usually is no room for a full GND plane and some sort of compromise is the result.
Also: How to achieve proper grounding youtube video from Rick Hartley is (over two hours long) worth watching.
I make net-tie footprints with PTH holes and then inner layers are connected. Just a couple of overlapping oval or rectangular pads for example. Throws drc errors that I ignore (could write a rule I suppose).
and here you see it on top and inner-1 layers:
Thanks again paulvdh. I took a look at all your links. I’m yet to tackle the 2-hour video but will do that too.
Here’s the Analog Devices schematic and layout guidelines:
I’ve followed the layout guidelines closely but now combined the 2 grounds. Heavy and fast switching currents will be localised to the top left.
The controller is in a “quieter” area of the PCB.
Top layer is Vin, Vout, GND and high-speed switching path (MOSFET drains etc). Second layer is the same. 3rd layer is MOSFET drains etc, Vin and Vout. Bottom layer is same as top and 2nd but with a lot of tracks from the controller up to the MOSFETs and sense resistors. There are some bypass capacitors on the bottom too to save space on the top.
I’m looking at providing dedicated return paths for the gate drive currents.
Define the footprint as a net-tie. Net ties are designed for this.
Hey Paul – I still don’t quite get net-ties, but started a new thread:
https://forum.kicad.info/t/net-tie-drc-errors/52429
You can text edit the kicad_mod footprint file and change the layer “Top/Bottom” → “Inner” as shown
The example footprint file is attached
NetTie-2_SMD_Pad0.2mm.kicad_mod (1.4 KB)
Thanks, that is nice! I was not able to get your file running, but I tweaked an smd net-tie from the kicad library to make it 4-layer and it works well. I will post it in the other thread I started on net-ties.
That is indeed nice. I’ve gone away from having separate signal and power ground planes but it I ever need it I know what to do.
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