I’m creating a PCB and some nets do not appear to be created in the PCB. I normally use the update PCB from schematic icon to perform the task but after several attempts check that connections actually did exist I decided to try a netlist export/import for more information.
The nets actually exist in the net file (two of them extracted below)
But the nets don’t show up in the PCB when I import the netlist. They don’t show up visually (even when moving components) and if a route from an involved pin all no-net pins highlight.
There are no errors on the import (either from netlist or from schematic). I’m at a loss as to what to check for.
Additional info: The netlist import stuff is not really how one should syncronize between eeschema and pcb_new under version 5. Use the update pcb from schematic tool for that. (found in the top toolbar for v5.1 or in the tool menu for all v5 releases)
Both together make up a symbol library. The lib file holds the symbol information (graphics plus fields) and the dcm file is for documentation stuff. Things in the dcm file can be different between aliases of a symbol. (This is there for legacy reasons as in the past this meant one could see crude info about all symbols in a lib without needing to download the full library file.)
It is definitively a strange way of doing things but the pin number can be any string you like. (KiCad 4 had the limitation of 4 characters but that is lifted with version 5.)
KiCad is case sensitive. You use TIP1 as the footprint pin number and Tip1 in the symbol. What is strange however is that the import tool does not report this as an error like it would if the pin numbers are completely different. This is clearly a bug.
Another strange thing is to use a filled polygon for the courtyard definition. It seems to work but is not how it is expected to be done. (Use the normal graphical tool to draw it instead of the polygon tool.)
@pedro Thanks for trying and @Rene_Poschl ahHa! thanks. Yes if it had complained about a mismatch I might have found it and it certainly would have been easier to narrow down. Clearly a bug as you pointed out and @eelik confirmed. No matter why a net isn’t formed when importing from the schematic it should obviously be reported even if it is net not created for unknown reason, it’s otherwise easy to miss a missing net. Maybe a DRC rule could check for consistency between schematic and board?
And, yes @jos it’s not the most common usage to have a non-numeric pin number but it’s not unheard of, even in IC packages. And this is not an IC package but an electromechanical one and those packages sometimes have no designation at all. So as an exercise to make this easier for other people to read I used a more verbose designation in this case.
I didn’t know that about the courtyard, how then does it then deal with objects that have inner areas that are not forbidden for placement?
I have noticed that KiCAD’s checks in this area are rather limited, there’s no equivalent to the courtyard for traces and vias for instance. Some packages require that vias not be placed in certain areas and some have areas where no Cu should be placed… There does not appear to be a way to check for violations of these restrictions currently.
First of all the polygon does not support cutouts so how would you make it with polygons?
And it works easily with normal lines by simply placing an outline for the cutout inside. see the rf_shielding footprints as an example. (Laird_Technologies_97-2002_25.40x25.40mm)