@eelik, I don’t think the problem is the via in this case because when the via would violate the real-time DRC, KiCAD refused to even draw the via and all I get is a trace that runs out from under the BGA. See my two photos in the earlier post. The via is being pushed away from the B2 pin. It is hard to tell in 4.0.7 which clearance is being used for any given pad or trace due to the inheritance, but by swapping clearance values in the net classes and footprint, it seems the problem is the pad. Here is another screenshot of routing a via between pads that are not connected (which belong to a different net class with a very small clearance). There is not problem and the via is snapping properly to the middle.
