Actually I don’t think we need anything new. Try:
(rule "42"
(condition "A.NetName == 'no_connect_*'")
(constraint clearance (min 0.0mm)))
(Make sure the rule is near the bottom of your rules so that it will override any other clearances defined.)
Note this solution will only work for pins that are not connected in the schematic and imported by netlist. It will not work for footprints created in PcbNew without a matching schematic symbol…
I’d claim that’s good. I don’t want clearance going to zero unless I specifically said it was OK.
Just tried this:
(rule "No clearance to Not Connected PINs"
(condition "A.NetName == 'no_connect_*'")
(constraint clearance (min 0.2mm))
)
and it does not work. You have my test PCB, so feel free to try this at the gate driver.
EDIT: I created the issue as requested. We can discouss everything there.
WARNING: my performance optimizations to rule checking last night had a catastrophic error. Don’t expect anything useful out of last night’s nightly if you use rules…
[Edit: I have pushed a fix if you build your own…]
I dub it the Anarchist's Release. 
Thanx for the heads up.
Three questions to guide my design:
I am design a board with some options to assembly the power regulation (linear or switching). To save board space and force only one to assembly, I am using one footprint over other in the board region.
I am also using hierarchical page design and thinking.
In case of re-annotation / change of reference values of some.
${foo:REFERENCE} variables.I’m not sure about the courtyard question, @JeffYoung?
Not directly (this is somewhat related to the Rooms feature planned for V7). I think the only way to do this in V6 would be to use special symbol fields unless Jeff can think of another.
Yes you need to be concerned about this, there is no automatic way to update if you have a rule referencing U10 and you reannotate it to U20. Then again, this has also been my experience with commercial tools 
If you like to reannotate parts after you start layout, I recommend not writing rules that use part references personally (there is usually another way)
No, but you can exclude the error. Just run DRC, right click on the error, and select “Exclude this violation”.
I am design some resistive voltage divisor for measurement
I want to put a progressive track-to-* clearance restriction with exception of the next voltage point (e.g. v0+ to v1+, that have a lesser voltage diference). The aggravating situation if that I use few of this circuits inside hierarchical blocks. So, the rules that I designed use * operator and are:
(version 1)
(rule measure_v0
(constraint clearance (min 2.5mm))
(condition "(A.Net == '*v0+' && B.Net != '*v1+') || (A.Net == '*v0-' && B.Net != '*v1-')")
)
(rule measure_v1
(constraint clearance (min 2mm))
(condition "(A.Net == '*v1+' && B.Net != '*v2+') || (A.Net == '*v1-' && B.Net != '*v2-')")
)
(rule measure_v2
(constraint clearance (min 1.5mm))
(condition "(A.Net == '*v2+' && B.Net != '*v3+') || (A.Net == '*v2-' && B.Net != '*v3-')")
)
(rule measure_v3
(constraint clearance (min 1mm))
(condition "(A.Net == '*v3+' && B.Net != '*v4+') || (A.Net == '*v3-' && B.Net != '*v4-')")
)
Does this make sense? If I understood correct…
How to use this rule to make those net distances to other elements? (board edge, etc).
Looks correct to me, though I haven’t tried it…
@JeffYoung it great to see new rule-based DRC. Way back we discussed BGA escape routing. I am not clear on this in the new rule-based system. Is it possible to have an area around a BGA with one set of rules, and then another set outside that area? For instance, traces at 3/3 under a BGA, then 3/5 outside the BGA area.
Yes. We renamed “keepouts” to “rule areas” in 5.99 precisely for situations like this: you can now create a rule area, give it a name, and reference it in DRC rules (those rules don’t necessarily have to be keepout rules)
And still this is unanswered. Here’s an example:
Here’s the rule:
(rule ldsfkj
(condition "A.insideArea('castellated') && A.Type == 'pad'")
(constraint edge_clearance (min 0.0mm))
Basically it should work (at least according to my personal logical intuition) but it doesn’t.
EDIT: not allowing overlap for two copper items of different nets makes sense. But it should be possible for copper/edge. Maybe a new keyword for edge_clearance, for example ‘allow_overlap’ or ‘ignore’ or ‘none’?
(constraint edge_clearance (allow_overlap))
Basically what you are asking for is to create conditions where some checks are completely disabled. This is useful for a number of scenarios but I think is not yet possible.
For 6.0 your best bet will be to mark these violations as ignored, I think.
Unfortunately it also means I can’t conveniently route castellated pads. This can be very counterproductive. One castellated edge can have tens of pads and each one has to be routed using highlight collisions mode.
@JeffYoung are there any easy fixes here?
I think this is “kind of” a regression, as the router didn’t look at edge clearance before. Can we easily change it so that clearance <= 0 allows collisions?
Well, 0 might have meaning (“no clearance required, but collisions not OK”).
It would be very easy to have < 0 disable the edge-clearance test, but it sets a precedent that it might work elsewhere (and it might be much harder to implement for the copper-clearance rule). I was sort of hoping for some flash of inspiration that didn’t require “magic” numbers…
That’s true. I think the best way would be to add a new keyword and allow you to say (constraint edge_clearance disabled) but I’m not sure how invasive that would be.
I have committed a change which will interpret a negative clearance as disabling the checks for:
Report bugs in the usual place…