First of all, thanks for your support!
Yes. Thanks, that helped.
I modified your great approach to clearance. I do not need to check the hole_to_hole distance, but the actual clearance. So my code now looks like this:
(version 1)
(rule "Clearance between Pads of Different Nets"
(constraint clearance (min 3.0mm))
(condition "A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net")
)
For my testing, it seems to work now. Thanks @Fabio_De_Bernardi!
If someone wants to contribute DRC examples that are added to the example section, please feel free to contribute:
Is there a constraint for footprint placement? Is KiCad setup to disallow footprint placement if it violates rules? I can’t seem to see if there is one.
You can create a polygonal Rule Area and disallow footprints, there’s no need for written rule. Do you need something else?
AFAIK KiCad doesn’t check any rules or constraints while a footprint is being placed. It would be nice to be able to do a real-time check with Highlight Collisions, but that would be a new feature wish and not part of the rule system directly.
I still don’t have an answer to this.
Jeff, you have changed something with hole related clearances recently (https://gitlab.com/kicad/code/kicad/-/issues/6882). Would you mind explaining what those clearances should do? I tried things for https://gitlab.com/kicad/code/kicad/-/issues/6894 but clearances for hole/copper don’t seem to work.
Those changes are so that the router respects hole clearances (and hole-to-hole clearances) while routing.
6894 doesn’t work because hole clearances aren’t tested within the same net.
What’s hole clearance vs. hole-to-hole clearance? Is it hole-copper clearance?
Implementing 6894, i.e. hole-edge to copper-of-another-item-of-same-net would make life easier.
Yes.
… … … …
Hi! I’m trying to create a ruleset for JLCPCB yet I have problem with several rules. After I have done what I can, I will post here for a check and then we can post it to related GitLab issue (though I am not sure if issue tracker is a good way to do this)
But before losing my mind and forgetting this, I have to give a couple of feedbacks right now.
At some point, we need to
I have quit without saving (and losing what I wrote) several times until now because word completion constantly interferes (which is acceptable and actually pretty cute) but pressing ESC (muscle memory, right?) closes the window without saving. Another save button may not be compliant with how “Board Settings” acts, hence separate window. Though putting a save button AND making ESC key quit word completion instead of window would work well, too. Dealer’s choice.
Having said those; good work! ^^
I have something like that in my (ongoing) ruleset, but there seems to be a little issue.
This seems to need a check if A & B are in the same layer, but checking for that condition will make our rule too long. Here is my attempt:
(rule “Minimum Spacing (Inner Layer)” (constraint clearance (min 0.127mm)) (condition “A.Type ==‘Track’ && B.Type ==‘Track’ && A.Layer == B.Layer && !A.Layer_Bottom && !A.Layer_Top”))
(rule “Minimum Spacing (Outer Layer), 1oz & 1/2 Layers” (constraint clearance (min 0.127mm)) (condition “A.Type ==‘Track’ && B.Type ==‘Track’ && A.Layer == B.Layer && (A.Layer_Bottom || A.Layer_Top)”))
I am not sure about “(A.Layer_Bottom || A.Layer_Top)” but it passes validation 
Also diving deeper, it seems like we may need “DRC presets” to keep track of variations somewhere in the future: JLC_2Layer_1oz, JLC_2Layer_2oz, JLC_4Layer_1oz, etc.
@vdaghan Use layer outer instead, simplifies much.
Wait, why do you need to specify the layer?
Why don’t you just use normal clearance specification, without that pad thing?
I also have a question (@eelik or @JeffYoung): How to address non-connected NC pins of ICs?
EDIT: @vdaghan please open a seperate threat for the drc rules for jlcpcb. I am happy to contrubute to those rules.
One more question: Is there the possibility to assign priorities to the rules? By priorities i mean not, how they are evaluated, but the order they are checked. E.g. i want to have pads first checked, then tracks. (Because when pads don’t fit, i need to redo the tracks anyway…)
Makes sense. Autocompletion did not have “layer bottom” so I went with this.
Assume that my board works if and only if it is manufacturable, i.e. no interference etc. Without specifying layer, I can’t make two traces which are coincident but on opposing layers pass DRC. Even if DRC accounts for board thickness, if my clearance spec (say, 3mm as above) is more than my PCB thickness (say 1.6mm), I can’t satisfy distance/clearance condition for a perfectly working PCB.
Now assume that I have a ground plane which magically negates any interference (which exists in this case) on a 4 layer board of 0.6mm thickness. Then I can put these two traces as close as ~0.6mm only if they are on opposite sides -possibly perpendicular-, but I may need to place them as far as 3mm if they are at the same plane.
One may argue that DRC does not check trace clearance for different layers, but I think it should -at least at some time in the future- check that. So we should account for it. Does this make sense?
Because JLCPCB, for example, uses different specs for pad-to-pad, via-to-via, hole-to-hole, etc. clearances.
Sure. The point was not a “JLCPCB ruleset” per se, but rather a “complete real-world application” of DRC which, in this state of things, making me a Guinea pig.
Thanks for your offer. I will try to make a test board in a couple of days and open another thread.
There’s lots of smarts in the DRC algorithms outside the rules. Things like layer checking, same-nets checking, etc.
In particular, the constraint “clearance” is for electrical copper clearance, and only applies to things on the same layer.
@overthere, what in particular do you want to address regarding a NC pin? (They don’t in general make it over to PCBNew, being trimmed out of the netlist on the Eeschema side. At least if I remember correctly.)
@craftyjon, remind me where we ended up with NC pins. They’re not in the netlist, right?
We talked about differentiating NC pins from just pins with no connection, but I don’t think we’ve done anything for it yet?
@JeffYoung they used to be excluded from the netlist but now they are included as no_connect_xx - you added that I think But, since you can place footprints and assign nets in PcbNew without a netlist or schematic, I’m not sure how useful that is here. We may want a hasNet() helper or something like that.
Oh yeah. That should help us here…
Can you please suggest how to formulate the propper condition term, if implemented… (Btw: If I should create an issue again, please just drop a note, and I’ll do…)
It probably wouldn’t hurt to have an issue just so that I don’t forget to look into it. It doesn’t need to be highly detailed or anything though…