I put down 9 pads in the right place and then drew a copper polygon over the pads to connect pads 1,2,3, 6, 7, and 8 since that is what the drawing shows. I am sure it will work. The copper is where I want it. and the paste and mask layers look right.
The net inspector does not like that. I am getting clearance errors, and solder mask aperture bridges items with different nets, (They are not different nets, they are the same net, and have the same name in the symbol.)
How do I do this to make the inspector happy?
I was thinking of making one pad for what is now 6 pads, and changing the solder mask and paste layers so that it appears to have places for the 6 pads.
Just to clarify, a screenshot of the linked to datasheet:
Having such a package defined as having 8 (or 9?) pins may make sense from the view of the package, but for the electronics it does not make much sense to me.
Just now I’m looking into the MKS Servo 57D project (on github) and it uses weird schematic symbols (drawn in some other, unknown, but not KiCad program), that look like:
It’s a sort of logical conclusion and the “easy way out” for such things.
I would do it differently in KiCad. I would just use one of the standard MOSfet schematic symbols with just 3 pins, and design the footprint according to that. It’s quite easy to add a graphic shape to a pad in a footprint, but overlapping and/or connected pads in the same footprint are a nuisance for KiCad.
I also see no advantage whatsoever to put all those pins in the footprint itself. If you’re ever going to refactor your design, you may use some other fet, with different pin assignments, but it will still have a gate, source and drain connection. So using just those 3 pins would leave the schematic unmodified, but then just design a new footprint for the next fet.
In V7, I have similar footprints, where in footprint properties - clearance overrides and settings, I have used the net-tie function to create a pad group.
In your case this would be 1,2,3,6,7,8
I will have to sort of agree with @paulvdh but a big question is who/how will the board be assembled?
If you will be doing mass production, then coordination with a manufacturing engineer involved with the assembly process might be a good idea.
But for hand assembly, I certainly would forget about all of those pins and just do something simple. I do not think I have used PPk ChipFET in KiCAD. But I previously used ExpressPCB and I do have a Power
Pak ChipFET footprint which I have used. The big drain pad is 2.97 mm square. It is oversized but I like that for hand soldering.
Holy (no)smokes. That is some serious heatsinking. I would normally just make my drain pad part of a larger zone on the top copper layer.
I think that these FETs will most often be used as high frequency power switches, so should not be grounded in that case anyway.
In that situation there is sort of a tradeoff. We want enough copper for heatsinking but not large enough to introduce excessive capacitance and produce more noise.
In footprints, the net-tie permissions allow different pads to be touching and on the same net without DRC complaining. In my post above you can see 5,6,7 & 8 are shorted
How did you connect pads 5,6, 7, and 8 without errors?
footprint opened in footprint editor → doubleclick empty canvas space → get footprint properties dialog → select second pane “Clearance overrides and settings” → look at the middle/bottom, section netties → insert new entry (“PLUS”-button) → type 5,6,7,8 ENTER
Interesting, I would never come to the idea to define in the footprint/pads that different pads should be shortened. in my opinion this should be done in the schematic or in a case like this here even in the symbol with hidden pins overlapping and therefore connecting to each other.
I have not made a PPk Chipfet footprint in KiCad, but this is an image of my footprint in ExpressPCB which I would have made years ago. It works well for hand soldering.
