Can't route tracks to specific pad

[Nadav1321]

Hi,

I’m trying to route a track to the NMOS pad and it doesn’t work and become green, it says: “The routing start point violates DRC” as shown below:

Thanks if anyone can help

[Nadav1321]

This is the DRC results:

[paulvdh]

You probably have interference between the 4 drain pins and the thermal pad in the center of the fet.

It is very similar to the topic below:

Need advice on a footprint PowerPAK ChipFET Single

I am using a SI5448DU-T1-GE3 Mosfet I am having problems with the footprint. The Datasheet is: https://www.vishay.com/doc?76149 My first pass did not work out so well. I put down 9 pads in the right place and then drew a copper polygon over the pads to connect pads 1,2,3, 6, 7, and 8 since that is what the drawing shows. I am sure it will work. The copper is where I want it. and the paste and mask layers look right. The net inspector does not like that. I am getting clearance errors, and s…

My personal preference would be to use a standard 3 pin Fet schematic symbol, and modify the footprint to fit with that.

[RaptorUK]

Not trying to be picky . . . that is the ERC result you have shown.

Can you show the details of the footprint you are using . . . or better still ZIP up the project and upload it here.

[Tojan]

looks for me like you haven’t connected the thermal pad with the drain in the symbol. you would need another pin in the symbol with the same pad number as the footprint has for its thermal pad. In this case I also would recommend to make only one pin visible in the symbol, make all others invisible and stack them on each other so you always have all drain pads connected.

Another option I like to use is to give the smaller pads and the thermal pad the same pad number in the footprint as they are anyway connected. then I only have to have one pin in the schematic symbol.