Hello there!
I am learning and working on design a rv1126 board with KiCAD.
This is my ever first try to design a SoC board with high speed signal (DDR) routing.
I want it to be a minimum system in a full-size mini PCIe card form factor ( now I think it may not be easy or impossible to put all components inside it, but I still want to try)
Please give me any feedback! Thanks
For people reviewing my design and teach me, I decide to share my work under CC BY-SA license
I checked out your link. But with my work being power conversion, I do not know much more after checking out the link than I knew before checking out the link. But I do think that your request is probably worthy and I hope that adding my useless chatter might help to increase interest in the discussion, much as it might do with (anti)social media. Once you get some intelligent answers we can delete this post. It has done its job (or not.) 
There are three main ways to reduce the size… 1. Reducing the size of parts from 0603 to 0402 to 0201, etc. 2. Increases the number of board layers. 3. Installation of parts on both sides of the board. The third method is the most expensive in production and all of them can be combined among themselves.
thanks！
You can take a look at screenshots in the project page.
The main problem is SoC emmc, two ddr chips and pmic are all large
I think @m852 forgot way #4 that is the most expensive - blind and buried vias. This will allow you not only to mount parts on both sides of the board, but to have overlap in those large footprints while breaking them out into inner layers. You would likely have to go up to 8L too.
No, I haven’t forgotten… Today it is not the most expensive method of manufacture… There are several implementations of non-through holes… For example, one of the https://jlcpcb.com/help/newsdetail/32-Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFV
Try to follow the basic rule… All large and heavy components on one side of the board are all small and light on the other side of the board… Otherwise, there may be production problems when the board passes through the melting furnace
As you are mentioning Via in Pad, JLC has make this method free for users, are there any pitfalls when to choose to use it? for example vendor-lock (higher price by other manufacturer)? expensive in small amount production?
The installation of parts on both sides of the production board is two separate devices in terms of cost, except for a few points… If we compare the cost of a multi-layer board with blind holes and mounts on both sides, then the first is cheaper in the end, all other things being equal.
For some RF devices, ordinary boards are not suitable FR-4 more expensive material with a specific wave resistance and other parameters is used there… In this case, the technology RF by reference is not suitable I think you understand why?
Thanks for tips! I’ll compare the cost of SMT
You have enough space for full placement try to make a trace using general design rules, this does not mean that they are mandatory in this case you need to simulate… General Rules I wrote to you above
Fan out SoC by hand ( I know there is a plugin to do it automatically, but I want to do it as a practice )
I found KiCAD does not support drag diff pair, I cloned the source code to see whether I can put such a tool for that
I found a standard mPCIe board is too small for my capabilities. I have to try to switch to larger size, 96boards as an example.
And I think I should change the board physical stack up to 1.6 mm
Changes to my new stackup
Setup new custom Rules as the stackup
Basically a 6-layer (that’s where JLCPCB offers plugged vias) PCB costs 3x @Pcbway and they do not even mention plugged vias (at a first glance). So: yes, you will be chained to JLCPCB unless you want to spend a fortune.
For people reviewing my design and teach me, I decide to share my work under CC BY-SA license
