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This forum is for questions around using KiCad. General questions about PCB design/best practices are discussed as well as they come up. Every now and then a PCB is posted here for discussion.
I cannot see this from your post.
Maybe you are better off with forums dealing with projects as a whole (hackaday, eeblog, contextual electronicsâŚ)?
Hi Eric1,
Honestly youâre not even doing a good job of gaining publicity for your project since that appears to be your motivation. As github itself comments on your repo: âNo description, website, or topics provided.â And I may add, no license.
In addition your repo is full of old files from previous versions of KiCad.
Perhaps you should spend some time writing up your project on a site like Hackaday.
I had a peek at your project, and it looks quite good. Especially the schematic is drawn in a very neat and clear way. It was a bit of a surprise to see over 700 ERC violations (Schematic Editor / Inspect / Electrical Rules Checker). Quite a lot are silly (Error reading simulation model from symbols âH1â (which is a mounting hole. Duh!) But ignoring ERC violations is a bad habit. With so many violations itâs easy to miss some important violations too. I guess you did not use ERC much at all.
It is also quite clearly one of your first projects in KiCad. KiCad is a bit *&^%$#@! concerning the use of the grid and connections. I assume you struggled a few times with this during this project. It really is best practice to never ever use a grid that is smaller then 50mil in KiCad schematics. This can be repaired relatively simple by:
- Set the grid to 50mil.
- Select everything on a schematic sheet.
- Right mouse button and select Align elements to Grid.
Although in this case, it also mis-aligns a few of the hierarchical sheet labels (but that is also quite easy to repair).
With a vector bus, you should use only two dots, not three, that is not a valid bus name in KiCad:
And also the reason KiCadâs ERC complains a lot about other bus labels.
There is a small gap in the bus near J1:
KiCad does not recognize this âNo Connectâ flag. The hint is that it still shows the little open circle. You should fix things like that.
Those things already get rid of the majority of the ERC violations. You should have a look at the rest and do some more cleanup.
About the CAN driver, you have R62 as a termination resistor. Termination resistors should not be placed on âBus Nodesâ, but only on the ends of the physical bus wires. Otherwise, a lot of nodes on the buss will load it too heavily. Often this is handled by putting some jumper in series with the termination resistor, or not placing the resistor in nodes halfway the wire. I donât know whatâs going on with R13, C13, R14, C14. I am not familiar with their use.
There are a few overlapping texts (on different sheets). I have seen far worse (the schematic really looks above average overall), but those overlapping texts should be cleaned up a bit.
But this is not a full review, just pointing out some âobviousâ things.
About the PCBâŚ
It looks quite well designed, especially for a first project, but some remarks here too. The most obvious is that the GND plane is not good. On a 4 layer PCB that is relatively low density such as this one, a full continuous layer should be dedicated to the GND plane, with no tracks on it at all. You have cut all the GND planes on each of the 4 layers to pieces with tracks, and this is not good.
Next thing: PCB Editor / Inspect / Design Rule Checker shows over 500 violations. some are silly, other may be more serious, but get obscured by the list of silly violations. How often did you run DRC? You can get of a lot of the Track has unconnected end with: PCB Editor / Tools / Cleanup Tracks & Vias.
You have made a weird âneck downâ connections around J2:
There is no need at all to do this.
You have used 16mil (0.4mm) wide tracks nearly everywhere. This is much too wide. Narrower tracks are better for all low current signals because they have less capacitance. A track as narrow as 0.1mm can already handle 400mA. An often used guideline is to use tracks that are about 30% wider then the thinnest your PCB manufacturer supports. Usually that is about 0.15 to 0.2mm. Also, 4 layer PCBâs are often made with tighter tolerances then 2 layer PCBâs (this is a part of the price difference). So look up the specifications of your PCB manufacturer.
There is no solder mask cutout for Q1. It will not get hot and you can screw it to the PCB (soldering is more common). But you also have tracks running under it. Solder mask is not an isolation barrier, so you need some other isolation here. While you might as well just make the area under that transistor free of copper, or fill it with the same net as the tab and then solder the tab to the PCB.
Same for the battery holder. You can not rely on solder mask to be an isolation barrier. Especially in vibration prone locations, you may wear though it and at some time cause a short circuit.
You have put viaâs though pads of some of the SMT parts:
This is very bad for automated production. For hand soldering this does not matter much, as you inspect the solder joint during soldering and add more solder. But when using a solder stencil, the amount of solder paste is fixed, the via sucks up most of the solder and there propably is not enough solder left for a reliable connection.
The groups of 9 GND viaâs do not look useful at all. The first thing to clean up is to make a single good GND plane though. I have not spent more time on other GND related issues.
Another quite important issue is the long rows of viaâs. They may look âneatâ, but they cut a big slot in the GND plane, and this is bad for EMC and signal integrity. Scatter those viaâs around a bit, so GND goes in between them.
DRC has some 150 to 200 âlibrary issuesâ
Net Classes!!!
You have not set up any net classes for your Board Setup. Learn how to use these! With net classes you can automatically route different tracks with different widths. Net classes are a quite essential part of PCB design.
You have a clearance around the WiFi antenna, and it may be âadequateâ, but I guess that giving the antenna more free room is (nearly?) always better. Maybe put the ESP module closer to the edge of the PCB to give the antenna more clearance. (I am not an expert on RF stuff, and am guessing here).
Nice logo, and a Revison number too. 2.3.3.3 ? How long have you been working on this project?
Another small thing: Put all electrolytic capacitors in the same orientation. (For example GND on the left side). This does not make any difference electrically, but it makes the PCB easier to inspect and check for errors.
And as retiredfeline noticed. Your git repository needs some cleanup too. You only have one git repository, and are apparently only 4 days on github. How much experience do you have with git?
Making an introduction of your project, put some catchy graphics on the first page both helps with inviting people, and with showing them quickly whether your project is of interest to them.
Putting a license on the thing is also quite important. Without a license, by law it defaults to âall rights reservedâ, and I guess that even my clone to do this review would be illegal officially. Lawyers make a mess of the world, donât give them any excuse to make it worse.
And there is a lot of crud in your git repository.
- Old KiCad files (.pro from a previous KiCad version)
- *.sch-bak files (and others) which are redundant and should not be in git at all.
- A backup directory with 9 previous versions of the project which should also not be in git.
This took me over an hour to type. I hope you make some good use of my time.
That is not all, but if you fix those things, your project is in much better shape and the feel of a âbeginnersâ project is gone.
Espressif specifies a clearance of at least 10mm around the antenna area.
Thereâs nothing wrong about discussing the project and closely related things here, but this went reeeeeally offtopic, so I deleted most of the discussion. Please continue ontopicâŚ
Also, you just posting a github link without any text with it puts off a lot of people. I even got a PM from another forum member asking me why I even bothered to put time in this.
All those responses are typed by people, and they all have their own set of feelings,emotions, motivations etc. And when you show you put some effort into presenting your project, people are more inclined to yelp you.
Take for example this project from Architeuthis-Flux. When you go to the github page you see a lot of pictures and even a .pdf of the schematic directly on the front page of the project, and this gives you an excellent and quick overview to decide whether this project overlaps your interests.
I wondered too tbh. The OP places one near empty post with a near empty link containing his epic brilliant design which we all need with 0 explanation.
At that point I already suspected that he would not be even comming back to read any answers or post a reply. Perhaps he may suprise us in a week or so, who knows? I still think we have heard the last of him.
I always recommend to verify if a new user is âableâ to respond to comments. Before investing your precious time. How hard does it suck to spend 1 hour of your time for nothing?
If somebody is too lazy to add any explanation or description at all here or @ github, than why bother to respond at all? Especially if his magnificent design has only a few 100 DRC and ERC error. If I would be mod I might even have deleted the thread entirely. And send him a PM.
Kind regards 
Bas
No.
It is not spam. It is not offensive. It is not off topic. It is Kicad.
He gets a chance. 
I also do not draw such conclusions within a day.
And after a few days my attention has probably wavered to some other topic anyway.
Maybe we even scared him off with the âoff topicâ thing that got started here.
Ok, pausing would be much better dan the digital bin 
Maybe he got fired for putting proprietary info openly on the Internet . . .
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