The solder mask clearance is almost twice the size of the pads on my SMD 0402 capacitor copper pads (they extend 0.15mm each side). When I don’t use thermals with copper pour it means pads connected to ground via ground plane will effectively be twice as big as long as solder mask application is perfect. What is the preferred way to have my pads as close to the footprints copper pad as possible? I read that recommended solder mask clearance is 1mm, while some fabs do 0.5mm. The clearance is set to 0mm by default in all settings, and when I edit the components with footprint editor I can’t see the soldermask layer. It’s on, but I can’t see it?
I just found the global setting for solder mask clearance, so I’m good with that. The question about if thermals are recommended or not is still of interest, though. Because I found when using thermals I never got the copper pour to pour as I wanted to.
Accuracy for soldermask for Chinese fabs is 4 mil (0.1 mm) on standard orders… western fabs should be able to do 2 mil (0.05 mm).
My last orders were set to 0.2 mm and came out fine, even a bit large… might drop it down to 0.1 next time.
Do you solder SMD 0402 per hand or reflow?
If you do reflow (or even have them assembled) you can drop the thermal relief for pad connection IMHO It depends… (*).
PS: You can set the soldermak clearance at 3 points afaik:
- per pad (prio 1) in FP editor
- per footprint (prio 2) in FP editor
- per board (prio 3) in PCBnew
If any of those points have ‘0.0’ as clearance setting, the next (lower) priority level setting takes over.
Thermal reliefs on a PCB are to make it easier to solder and desolder
thru-hole components when you have a circuit board with internal planes,
large poured planes, or wide conducting traces. Without the relief
patterns on copper planes (or wide traces), the planes (or traces) act
as a heat sink drawing much of the heat away from the lead you are
trying to solder or desolder. The result could be a cold solder joint,
or the need to apply excess heat while soldering. Often it is
impossible to desolder a component without damaging the board if that
component was placed without thermal reliefs on the large connected
Section 9.1.3 of IPC-2221 “Generic Standard on Printed Board Design” says:
9.1.3 Thermal Relief in Conductor Planes - Thermal relief is only
required for holes that are subject to soldering in large conductor
areas (ground planes, voltage planes, thermal planes, etc). Relief is
required to reduce soldering dwell time by providing thermal resistance
during the soldering process.
These type connections SHALL be relieved in a manner similar to that
shown in Figure 9-4. The relationship between the hole size, land and
web area is critical. See the sectional standards for more detailed
Thank you. I found both pad properties and footprint properties had solder mask clearance set to 0, so I went looking for the global one and found it in pcbnew.
I didn’t see from your quoted text anything about smd pads, only for holes, but I guess the same thing goes for them. I don’t care much about de-soldering, but did you mean the text said anything about hand soldering vs reflow soldering? I do solder the 0402 by hand on the first runs, but generally with a modern soldering iron I never experience any issues with large ground pads connected to large ground planes, so for hand soldering I don’t worry, only for when it goes to mass production.
The problem is essentially the same for SMD footprints that are soldered by hand: direct connections to copper pours, large traces, etc, conduct heat away from the solder joint, resulting in poor quality joints. It may be even worse for SMD devices, since the small pads don’t offer much surface area for the soldering iron to transfer heat into the joint. (Some designers even use larger SMD footprints for boards that are to be hand-soldered versus reflow.)
In a prior incarnation the production engineers asked for thermal relief on all pads, both SMD and thru-hole. They said it helped keep manufacturing results consistent, since all pads had similar thermal characteristics. Now that I think about it I don’t know if that was a valid argument or not. It may indicate marginal control over the reflow soldering process, or possibly just a holdover from old habits.
Follow the link - I stroke out part of my answer as it might be wrong advice.
Some of the replies after the one I quoted up there talk about SMDs tomb stoning, when one pad is connected to a large thermal capacity during heating/cooling - which in this case means thermal relief would be preferred for automated soldering of SMDs.
I didn’t encouter that yet, but my track record is pretty short
Also I only knew about thermal relief in regards to what I quoted up there - helping the hand soldering of through hole devices. The tomb stoning of SMDs was new to me, or I forgot it. So thanks in bringing this to my attention (again)
Yes, the thermal relief spokes tend to equalize the thermal behavior of all the pads on a board, so they heat and cool at roughly the same rates.
In over 20 years working with SMT assemblies I’ve heard a LOT of talk, and seen dozens of photos, related to “tombstoning” but have first-hand personal experience in only one or two cases. (I worked in design and development, not manufacturing, but I handed off dozens of assemblies to manufacturing and definitely heard from manufacturing whenever there was any problem affecting producibility, yield, or re-work.) In my opinion, “tombstoning” isn’t as big a problem as some make it out to be, or else it’s a problem with so much awareness and routine precautionary measures that it seldom has a chance to happen.
What I DID see with some regularity was “starved” solder joints. That’s where, after soldering and cleaning, there is either no solder joining a component lead to a pad, or so little solder that the joint comes apart under vibration, thermal cycling, or normal handling. Where a tombstone part is fairly obvious under visual inspection, you often need careful examination under magnification to find a starved joint. The really insidious thing is that a starved joint may initially make electrical connection due to physical contact, but later open up or become intermittent.
The majority of instances I saw were, to my mind, random occurrences. If, after going through stacks of rework logs and failure reports, the process control folks found any patterns, I never heard about it. I do recall two cases where board design was a factor. In one case the solution to solder-starved joints was to add more solder. (Rather obvious, eh?) The SMD pads, and their corresponding solder-stencil cutouts, were enlarged so that more solder paste was laid under the component, and more of it was exposed to the reflow heat source. In the other case a “large” component (both physically and thermally - a ferrite core inductor) was both “shadowing” a group of components from the reflow heat source, and serving as a local heat sink. Solder wasn’t melting to the point where it would wet the surfaces and flow into the joint. Fortunately, turning the board 90 degrees in the panel, and some minor tweeks to times and temperatures in the reflow process, solved that one without a major board redesign but it’s a case where SMD pad thermal relief could have been a contributing factor.
Dale, thank you for fascinating read. Could you express you opinion about the footprint I made according to the Microchip note?
Will I have any trouble with soldering by hand?
MCP73831 LiPo charger heat dissipation layout
Tom, I just now downloaded your project and popped it open. I want to find time to look it over this weekend, after I’ve had a chance to at least skim through the datasheet and application literature for the part. (I’m especially interested because I’ve recently done some battery charger and battery monitoring circuits.)
One thing I noticed right away is some silkscreen on top of pads in several places. In days gone by, a board actually fabricated that way was not usable in any automated assembly process, and difficult (at best) to produce a working assembly with manual soldering. Today, some fab houses automatically omit any silkscreen that falls on exposed copper areas. Others still put the job on hold until you correct the violation. (I don’t think the KiCAD DRC tests any of the silkscreen constraints when it checks a board. I hope that feature gets implemented soon.)
You mentioned enlarging the pads for the SOT-23 package. That is a general problem with ANY of the SMT parts. The pad sizes that work well with reflow soldering don’t expose enough bare metal for a soldering iron to make good contact and heat the joint. The problem is often not apparent until you create Gerbers, and overlay the component outlines onto the solder mask. Then you see that there just isn’t enough space for even a tiny soldering iron tip to get onto exposed metal adjacent to the component and heat the joint. I think one of the standard KiCAD libraries includes footprints for hand-soldering the common passive components (0805 resistors, 1206 capacitors, etc).
This very useful, I will change the circuit and the parts library, so that I cut out the offending silkscreen and move it to documentation layer.
Indeed, some library parts are in reflow and hand soldering flavor, but my very limited experience tells me to check each one footprint
You might try pouring a copper ground plane on the entire front, and use thermal relief. (Instead of what seems to be a ground plane poured around the edge of the front of your board, via stitched to a ground plane on the back.)
you don’t have your current concern about soldering issues
paths to ground may be shorter without needing so many via stitches
it requires less copper etching at the fab (less chemical recycling)
I know I’m not answering your question, but other readers may not know that you can sometimes pour copper ground planes on the entire front and back. Its a good first step when you are manually routing, since the ground net is often the largest net.
This is exactly how I do my typical boards. GND pour goes first. However in the case of thermal dissipation requirement, like lipo charger chip - do you think normal thermal spokes are ok?
I see your quandary: you use thermal relief so that soldering heat doesn’t escape, but you wonder whether the heat of the chip can escape through thermal relief spokes? This should be a separate thread if it hasn’t been covered already.
Thats a special case: when a chip has a thermal pad. Typically it should also be grounded. Think of the mating pad on the PCB as a radiator or heat sink. I typically need to design a new footprint. Typically I use a square (rectangular) TH through hole pad to accept the thermal pad on the chip. (Give the pad the same pin number as another ground pin.) The hole is plated and conducts heat to the pad on the back, which is not solder masked (is bare copper) and radiates heat. Then yes, I do use thermal relief and assume that is enough heat sink for the chip. One concern is that the hole (or holes) wicks all the solder paste away from the solder joint. Professionals plug the holes after plating. The pad on the back COULD be solder masked, I don’t think the thin solder mask is as much a heat insulator as the plastic of the chip. Another concern is the paste percent and pattern so that there are less voids in the solder joint. As a hobbyist, I don’t worry too much about these concerns.
Another approach is to not use thermal relief, and use a copper fill on the front that overlaps the thermal pad (as the OP did, but not for thermal reasons?) and extends out from under the chip.
Thanks, I understand clearly!
I still have lots to learn
For hand soldering there has to be enough pad sticking out from under the component that you can touch it with a soldering iron tip and transfer heat to the joint. If the pad is attached to some heavy traces, or a poured region, one of my favorite tricks is to touch the joint with TWO soldering irons simultaneously - which requires a little more of the pad to be exposed.
This design calls for components in SOT23-5, and 0603, packages. These are at the limits of what my trifocaled, superannuated eyeballs can handle on a routine basis. Especially the 0603’s. I don’t know what project this is part of, but if manual soldering is a requirement beyond a handful of prototypes, then think hard before going to smaller components.
I’m still playing with your board layout. The Data Sheet doesn’t give any useful guidance about thermal design, except to say the chip will protect itself if it overheats. (Yeah, right.) With power-related parts the manufacturer will sometimes tell you that a particular pin or group of pins is used to conduct heat from the chip to the outside world, but I couldn’t find that info for this MCP73831. Of course thee aren’t many pins to choose from so I’d nominate VBAT and GND as the thermal conduits. The smaller part, in the DFN package with the exposed thermal pad, might actually give better performance than the SOT23-5.
I went looking for examples of projects using this IC, with construction details. I didn’t find any, except for the Microchip Demo Board (see http://ww1.microchip.com/downloads/en/DeviceDoc/51596a.pdf ). The Demo Board’s layout is a little more open than your project’s, but not much.
So if I had to hand solder this project I’d start by adding some thermal relief to the input and output capacitors. In normal operation they shouldn’t dissipate much heat so a little more thermal resistance between the component body and the copper planes isn’t a problem.
The “GND” connection on the IC automatically has thermal relief, just because of the way you need to route traces to it. Likewise for the “STAT” and “PGM” pins.
That leaves “VIN” and “VBAT”. I’d like to add thermal relief - perhaps using 0.025" connecting spokes, and a 0.015" or 0.020" antipad gap as a first guess. But when you implement that, it tears up the continuity of those poured planes rather severely. So leave those pads connected directly to the planes, but make sure the joints get soldered VERY well.
(It may be important to have both a good electrical connection, AND a good thermal connection to those pins. I recently had hands-on experience with a much different IC, Linear’s LTC4011. It uses a thermal pad. Our initial prototype batch didn’t leave enough exposed pad for heat and solder to effectively flow into the joints. We ended up with joints that were tacked in place only along one edge of the thermal pad. 60% of that prototype batch failed within seconds of first applying power. )
The QFN has got 76 K/W and the SOT23 manages 230 K/W (130 K/W for large copper areas).
So QFN is better in any case.
Soldering the QFN reliably to get the at least 2x better thermal performance (up to 5x better) is another story tho…
Thanks! Great ideas, I will use them.
Ain’t that the truth! On just about any day, my superannuated tri-focaled eyeballs can do at least mediocre (or better) hand-solder work with SOT23’s and other packages with 0.95 mm pitch.
But this DFN package with 0.5 mm pitch - and NO leads - is two sizes smaller. Note that Microchip’s published footprint can’t be hand-soldered: the connection for the thermal pad is entirely under the package case, so you can’t touch it with a soldering iron no matter how hard you try. The thermal pad in the footprint needs to be extended so at least a sliver of copper sticks out beyond the part’s body.