Yep, that is precisely where I was going with this.
Precisely!! I think you hit the exact core of the issue as I see it!! That is the actual issue, and yes, I’m using labels to compensate for that (arguable) deficiency.
I don’t think hierarchical sheets would help. As you comment:
Well, I don’t want a global name for it. (I mean, assuming, as I understand it, that then in the layout, all the pins ultimately connected to VCC will show the same label).
[[ Side note: I am not familiar with hierarchical sheets (I did read about them a while ago, but never used them). So, please do correct me if I’m wrong on my interpretation above ]]
I claim that I want to maintain the original names (VCCINT, VCCPINT, VCCIO, VCCBRAM, etc.) because they describe the role, and not the actual value they happen to have. With power signals, in particular, this is crucial. Being on the same net does not make them the same for layout purposes: decoupling issues/constraints or propagation time issues (when working with high-speed signals) make each pin or area a distinct element that has to be treated (and thus labeled) separately. With the Zynq, for example, they specify decoupling requirements, and for example, they say that VCCINT (9 pins) requires 4 decoupling capacitors. Well, when the layout shows all VCCINT, VCCPINT, and VCCBRAM pins labeled as 1.0V (because I chose to use the same 1.0V power supply for these three VCC’s, which is perfectly ok to do), then I get lost on which are the 9 VCCINT pins for which I needed the 4 decoupling caps.
A similar situation is the following: I have a signal that I want to “hardcode” to 0 or 1 — meaning, connect to GND or VCC (which will show in the schematic as +3.3V). Say, an ENABLE that I want to hardwire to VCC, or a CS for an SPI port that I want to permanently disable, so I tie it to VCC.
Then, when I need to place the decoupling capacitor on the VCC pin, pcbnew shows me several pins that are all labeled +3.3V, so I have to go back to the schematic or the datasheet to determine which of those pins is the one where I want to place the decoupling capacitor.
So far, I’ve compensated for that deficiency by manually assigning the REF to the caps using the pin number. For example, if my MCU chip has pins 3, 7, 14, and 22 as VCC pins, then I name the capacitors CM3, CM7, CM14, and CM22 (M for MCU, to distinguish them from the decoupling caps of other chips). But that can get tedious and difficult to handle.
This has been a problem especially now with the Zynq, which (1) is a BGA so the pin names are longer; and (2) it is not a 1:1 decoupling cap : pin mapping; so, if anything, I would want to name them CI1, CI2, CI3, and CI4 to know that those are the four VCCINT capacitors. But then, I would need pcbnew to show me the VCCINT pins labeled as VCCINT, and not as 1.0V (or VCCBRAM, as it is doing now in my design!)
Hopefully this clarifies a bit what I’m expecting / suggesting.
I guess there are two possibilities:
- Netname aliases — with the ability to indicate which points in the schematic (pins, mainly) get which netname. @qu1ck suggested a rather clever way to accomplish this (and in retrospect, I think that’s what my brain was implicitly expecting to happen, without realizing that that would have to be explicitly coded in the software):
- Maintaining the pin names. Possibly the way it should work could be: the pad shows the pin name, and if one hovers over the pad, then it changes to the netname to which it is connected. (example: I see the pin with name VCC or VDD, and when I hover the mouse, it changes to +3.3V).
However, in some cases this may not work as nicely; many chips have really long pin names (case in point: the Zynq. Pin names can be
VCCO_MIO0_500, or something like
PS_MIO16_501/ETH0_TX_CLK). That certainly won’t play nice with this feature of showing pin names (maybe through the “tooltip text”, when hovering over the pad??)
As for traces and zones (as also pointed out by qu1ck); what’s the problem with showing all aliases to which they are connected? After all, there is (in principle / most of the time) room available, assuming the trace is long enough (and if it isn’t, probably wouldn’t matter not to show anything, since the pads to which it is connected are right there)