It would be even better if I could see it directly in the layout.
With the naming convention I posted earlier, you have the component name and pin number in the Refdes of each decoupling cap.
What more hints could you wish for?
As you may have noticed. My preference is to just put all decoupling caps in a row together, preferably on a separate sheet in the hierarchy.
With the automatic pan in Pcbnew, you can easily track where all the decoupling capacitors are, and do an examination of the whole quality of the decoupling network as a separate step near the end of the PCB design.
In my view, putting the decoupling caps on the schematic near the IC they are used for just clutters the schematic with noise that has no relation to the workings of the schematic itself.
After inserting all elements into PCB one of my first actions is to place decoupling capacitors near ICs.
Seeing each of them selected at schematic is so helpful that I donât feel any improvement is really important.
Then I move such sets together. I have never designed a huge schematic so I typically have about 10 such capacitors. It is so small work.
I think other aspects of pcbnew are more important to work on them.
The problem is that it may be very tricky to do so. See screen capture below (this is from the same project; the ethernet transceiver). How would you go about placing the capacitors near each VDD pin?
I still follow this idea, and place the capacitors near the target; but notice that I number them with the pin number, and in this case, the letter E (for Ethernet), and that helps me when doing the layout:
Separating the ânetâ into DVDDL, DVDDH etc is useless, except for very special circumstances (ADCâs and such, but then they are often real separate nets also)
General rule: More copper is less impedance.
Ferrite beads on an Ethernet controller?
This also takes care of the âseparate netâ thing for you.
What is the meaning of those ears on your capacitors?
They probably mean something, but itâs unclear to me (and probably other people who see your schematic).
With QFPâs on a dual layer boad I tend to put 4 decoupling capacitors in a cross, on the bottom of the PCB. which naturally forms a sort of local star ground point for the decoupling. With bigger ICâs you often see a shitload of decoupling caps on the opposite site below each IC. For example in the EEVblog oscilloscope teardowns. I do not make PCBâs of such complexity myself.
Yes, it has no relation to the working of the schematic itself, but I donât see it as a noise. I never use top and bottom of IC symbol for I/O lines. Having some power pins at top of IC symbol and decoupling capacitors there in my opinion donât disturb understanding of schematic working. And when I decide to use not only capacitors but also connect that IC to VCC through ferrite bead I just see looking at that IC at schematic that such filtering was used. If that would be placed at another schematic sheet it can be easily overlooked.
Many datasheets of ICs having digital and analog part specify for example the inductance, or ferrite bead to be placed between power supply pins. It is easier to check schematic regarding datasheet instructions when you have all filtering/decoupling elements near IC symbol.
I have seen sometimes such datasheets where the decoupling was printed separately form IC. In such situations it is hard for me to imagine where I will have that inductance - I have to drow it at paper myslef. It is important for me as I design 2 layer boards with all signals (except GND) at top. So knowing that I have an element that I can go with tracks under it is important for me typically even before I start drawing a schematic (at stage of planning where I will place what to allow for all connections be done.
Ok It is not easy. I have newer used IC with so many power pins. May be in that situation placing capacitors separately is the simplest solution (and may be the best).
I have once done it such way (not with KiCad yet):
There are other things to consider. My schematics are read really only be me so need be clear for me only. I wont all schematic to be one sheet (if only possible) because even so a printed collection of them becomes bigger and bigger. For me it is faster to look for the solution I used before for something by go through this sheets then to search at computer when Iâm not sure in what product that was used.
Because of âone sheetâ target I prefere to save schematic space whenever possible.
So I accept that you can not like my schematic.
I may have misinterpreted that question.
Is it about the schematic or PCB?
The last image Piotr posted looks OK on first sight, but in my experience when you strive for that kind of compactness on a schematic, you spend up wasting many hours in trying to fit everything, and multiple iterations of rearranging everything.
You change one capacitor from ceramic to Elco, and the text does not fit anymore, and you have another whole iteration cycle.
Also, this compactness is not very readable.
GND on left and right side of capacitors???
GND symbol upside down?
I find it a big mess. Just try to figure out which text belongs to which capacitor.
But peopleâs habits are different.
You also get used to what youâre used to.
My question/comment about the issue of prefering to have the decoupling caps close to the pins they connect to was referring to the schematics (I mean, for the PCB, thatâs not even a question and itâs not a matter of personal preference: the decoupling capacitors must be as close as reasonably possible to the pins they are decoupling).
Commenting on your last message: as Piotr indicated, he is only concerned with writing schematics so that he can understand them, so in that sense itâs all fair.
I do agree with you that one ends up spending too much time on the little graphical details on the schematic and ist ends up being more time than what you are saving while working on the layout. But I do see the niceness in the idea of drawing the schematic as he suggests. (so long as one doesnât take that idea too far)
Although now weâre getting into off-topic territory, I would ask that you indulge me with some more comments on why you are surprised and even sounding like it may be a bad idea to use ferrite beads on an Ethernet controller.
I myself am not a huge fan of placing ferrite beads; but in this case, Iâm following the manufacturerâs (implicit) advice. This is the KSZ9131RNX (from Microchip). The chipâs datasheet itself says nothing about this; but the evaluation board from the manufacturer shows the schematic and Iâm placing the ferrite beads following exactly the configuration they use.
Again, Iâm interested in what your thoughts are on this.
Thanks,
Carlos
Itâs common to see ferrite beads (and other filtering measures) on anything connecting to the âoutside worldâ.
Especially ESD discharges have steep flanks and these can upset logic, even if there is no permanent damage. Directly discharging into a GND plane can be problematic. You always have to think of how the currents flow through the GND plane, and can cause voltage differences.
With Ethernet you already have both galvanic isolation and a bandwidth limited transformer, and on top of that twisted pair cable which also reduce emitted noise.
Often the ferrite beads are not needed for the schematic at all but are purely for meeting EMI requirements.
It may be that for an evaluation board they wanted to be âextra sureâ to give the user a good experience. Evaluation boards also tend to be used outside of (metal) enclosures, and on the tables of engineers with lots of test equimpent on their desk and looking for a fault.
For all digital designs, a noisy Vcc is often not very important, but if you have mixed analog and digital, then keeping the power planes free from noise is one of the things to do to get the best out of your analog circuits.
Very thick (and expensive) books have been written about EMC and there are no easy answers that fit on a forum like this.
Never happened to me.
When tantals disappeared (I think 2002) I moved to use ceramic uF capacitors and still donât use tantals.
So the only electrolytics I use are the 2 big in DC power input filter.
Value change - also. Iâm sure that I wont one 100nF per each pin and one bigger (but also ceramic).
It would be a problem for me if I use the same graphic symbol for other power lines. But as I use it only for GND (or other GNDs) it never disturbs my understanding what is going on here.
My first try was to place VCC/GND pin pairs at top and at bottom of symbol and place capacitors between each pair (directly showing its intended placement) and connect each line to GND or VCC (so the GND and VCC symbols at bottom was towards down and at top towards up. But after some schematics done that way I changed my mind to the solution with all VCC at top and GND at bottom of IC symbol.
It is not so difficult, but does it really care if all are the same. I donât give the capacitors the numbers myself. I just use Annotate. The rule I use is the capacitors with higher number are placed at pin with higher number but in practice it is absolutely not important. I think no one even notices it when processing Peak&Place file to program the production.
And even when PCB is hand soldered prototype I think the PCB drawing with element values is used and no one (in our firm) looks at schematic. The contract manufacturer canât look at schematic as documentation we send him does not contain it.
I think it is only when you wont to made it compact. If you donât save place too much you donât loose too much time for it.
Interference suppression is most effective right at its source. I understand Ethernet IC as such source.
The inductances in my schematic are ferrite beads.
But when I went to EMC lab they said (it was lab owned by other manufacturer) that probably I have used better sockets with integrated trafos then they as they coudnât get under limits with their own products even having galvanic isolation and common mode trafo sockets they used.
So my understanding is that as farrite beads are now so cheep then one more donât cares but can keep you more safety.
It is not important for correct working. But it than have to be filtered to not be emitted by power supply pins. The less noisy VCC the easiest its filtering.
Ferrite beads are cheap indeed.
Failing an EMC test for a commercial product is not.
Just the delay in time to market could be disastrous.
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