Mixed mode simulation including C code and verilog

Schematic Simulation (Ngspice)
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I attach a basic simulation combining standard spice models, Xspice models, verilog using yosys and c-code using the d_process method. It’s my way of giving back as I’ve been using Kicad professionally and privately since version 4.

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The example is based heavily on The Easiest Way of Simulating C/C++ Code Together with an Analog & Digital Spice Simulation — ISOTEL. Hopefully between the two examples there should be enough for most people to understand what’s happening.

I only use Linux so the instructions will need modifying for Windows and possibly MacOS. Apologies for not being able to help with that. If anyone can get it running on those two, it would be appreciated.

The basic circuit is a simplified buck converter with a current controller. Switches are just switches with anti parallel diodes. No input/output capacitors, just voltage sources.

Target current is set in the buck_controller_msp430.c file and P and I gains are in the buck_fw_msp430.lib file.

You need Kicad 8.0.1, Yosys (tested with 0.23-6 on ubuntu), git and gcc.

To run, extract the files into a folder. Change to the folder and run “git clone GitHub - Isotel/mixedsim: Hardware Design Tool - Mixed Signal Simulation with Verilog” to get the Xspice models for yosys. Then run ./compile_all.sh. This will compile the c and verilog code. d_process.h has been copied from the ngspice source code.

Having done this, you can open the schematic, modify the control line “cd ~/Electronics/holger_sims/buck_msp430” with the folder that you put the files in and run the simulation as normal.

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If you open Kicad from a terminal then you can monitor the stderr output as simulation runs.

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A big thank you to all of the Kicad team! @holger I am always impressed and grateful for the help you give for how to use the simulation features on these forums. The improvements in ngspice over the last few years have also been very impressive. You’re welcome to take this sim and integrate it into your list of examples. You can also modify it as much as you want.

buck_example.zip (548.3 KB)

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Thanks for posting.

I’ll look at it, but it may take some time.

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@uros I believe that you’re the person behind Isotel.eu?

Thank you for your example c and verilog model. I hope you’re happy how I’ve used it to produce the example model in the first post above. Feel free to take it and use it to update your original example if you want a kicad example to go with your eagle one.

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Welcome and thank you for your effort for making a kicad example. I just recently started with kicad/ngspice integration and I am impressed by the progress.

As first I would create a hyper link to this use case.

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I am looking at current directory, which is not the project folder but kicad start-up folder. So you had to use an absolute path, which does not make a real sense.

I am not sure if anybody needs ngspice to start like this, whenever I’ve used I’ve always started it from the project folder, so it would make sense that kicad would also change default directory to the project directory. Also python console starts in the same way, but probably we can get the KIPRJMOD variable there and change it, which is not possible in ngspice.

Not sure what is others opinion but I would change default directory to project root not “system default”.

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Yes that’s correct. It needs an absolute path at the moment. Interestingly, you only need to change the working directory once per session. After the first run it remembers until you restart kicad.

I agree that the default working path should be the project directory. I haven’t got a GitHub account so haven’t started filing bugs.

I think that there’s also.a memory leak. After a few long runs kicad locks up and then closes.

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Yes as it changes kicad default/working directory.

So I’ve changed the directory in the python console, but there is another bug, that the KIPRJMOD is only set once PCB is open, added comment to past issue (environment variable KIPRJMOD fails to refresh (at least in python console) (#5071) · Issues · KiCad / KiCad Source Code / kicad · GitLab); so after opening the pcb and changing it in python the ngspice works

import os
cd( os.getenv("KIPRJMOD") )

Paths and project specific directives should be in .spiceinit file in the project folder, so changing the folder would benefit also in reading this file. There additional source paths may be added to find modules from mixedsim etc.

Anyway I see running ticket, on which I’ve commented: 7.99 Send project directory name to ngspice (#16527) · Issues · KiCad / KiCad Source Code / kicad · GitLab

On Linux an easy work-around is to start the kicad <project> from a command line directly from the project directory; but that’s not the way users would use kicad on win*.

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I’ve just filed a bug for a crash I keep getting with this simulation. If you run a 200ms transient simulation with 5us timesteps then it crashes before 200ms on my computer.

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Any idea why it crashes? Is your memory exhausted, do you have enough memory?

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I suspect it’s running out of memory. It’s taking up 11.2 GB of virtual memory for a 100ms simulation and I’ve got about 12GB available. If it is then I assume that kicad/ngspice is keeping the entire simulation result in memory and it would probably be better to write to a file and just read in what’s required like ltspice.

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ngspice will not automatically delete any results generated. You have to understand what memory usage is generated, what is to keep, what to store and what is to delete. You have full control over the simulator, and you have to make use of this control!

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I can understand that approach and I will dig into the details to disable saving as much as possible. I was expecting that this is probably a preventable issue.

However, the fact that with the default settings, kicad will just crash silently with this model seemed worth highlighting.

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It looks like I might also be running into another bug (issue 16404) where kicad doesn’t get rid of the simulation vectors when a new simulation is run.

I added pre_destroy all to the control section that partially sorts that bit out.

I’ve also turned off saving all data in the kicad analysis tab and added “save v(/hv_lu)” and “save I(v1)”.

When the simulation starts the memory is cleared however it still uses about 11GB (same as before) for a 100ms simulation. I was expecting the amount used to reduce significantly so have I misunderstood the commands or missed an important one?

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This circuit contains quite a lot of digital (XSPICE) instances owing to the yosys synthesis tool. This causes the simulation to generate large amounts of digital event data, by default, when it is run. If you do not wish to examine this mass of results via eprint, eprvcd, or plot, then those events do not need to be saved. In the .control…endc section of the schematic, you can include “esave none”, and then no event data results are saved. If you need to see events on only a few digital nodes, then select them individually using “esave <node> …” commands. I ran to completion your netlist for “.tran 5u 200m 0” with “esave none” and the max. program size reported by “rusage” was approx. 224MB. The analog voltage and current results should be the same with or without saving digital events. I hope this helps.

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That sounds like it’s going to solve my issue! Thank you!

I hadn’t realised that XSPICE had it’s own separate saved data but I’m not surprised that it’s enormous.

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Now that I’ve given it a go, I can confirm that “esave none” solves the memory issue. I see that I was looking in the wrong section of the manual. I was looking in the XSPICE section, not the interactive interpreter section. Looks like I’ve got a lot of manual reading to catch up on.

I’m now happy to use kicad and ngspice for power electronics simulations (and probably more). It’s reasonably fast and can replace most uses of PLECS and LTSPICE for me.