Mismatch between hierachical labels and pin sheet

I met a strange question on “Mismatch between hierarchical labels and pin sheets”, which confused me. Can anybody give me some help? thanks.

by the way, how can I upload a picture to show my snapshot? thanks.


Hierachical Pins on a Hierarchical Sheet should exactly match the Hierarchical Labels on that sheet when you open it. The warning is showing either a spelling problem or you have forgotten to add a Pin on the Sheet box

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Take a screenshot and then paste it (windows = Ctrl+V, Mac? Linux?) into the reply window.
If you want to modify it before that (remove IDs, highlight important stuff or resize a 3680x1280 desktop screenshot) use some raster image manipulation software like gimp or what-have-you to get that done.

@chen_yong_20000 is a new member and cannot post attachments yet.

ah, right.
@chen_yong_20000, read a couple of posts/threads and I think wait 24 hours or something like that… then you should be able to upload images to the forum directly.

Thanks everybody for your help. I’m not sure if I really do the right thing but I thought I’m. I have created a bus and connected this bus to a hierarchical lable. Then on hierarchical sheet I created the hierarchical pin with the same label name. Then I got the error. I will upload my screen snapshot to show my schematics 24 hours later.


Read the forum rules and you will get a badge. As Joan said, read some topics and you will move quickly to the next level, with posting rights

I think now I can upload my schematics. Please help me to find the reason why C_A bus are marked as “Mismatch between hierarchical labels and pins sheets … : sheet label C_A1 is not connected to a hierarchical label”.

chen yong

sorry, I’m limited to send one picture once because I’m a new user

And it is interesting that in test point sheet there is no error reported

I think you have some bad habits from Verliog :smiley:
Inside test_point sheet you use a CA[1..8] which is good notation, but in power_shift you use a CA[1:8] which is wrong notation.


OFF: For people who programming in C it’s a better solution when they meet FPGA’s.

Hi all,
when I changed C_A[1:8] to C_A[1…8], the error is gone. Thanks very much.

chen yong

Yes, I’m a asic/fpga designer. :slight_smile: