Making Progress...need some more help

Schematic Simulation (Ngspice)
1

I’m making progress with my learning curve but need a little more help from you experts.

I have a multi-stage amplifier entered as a schematic and am running a simulation intended to get DC operating voltages. I’m getting pretty reasonable output from the simulation, no error messages and a fair number of DC voltages that seem reasonable based on my circuit design.

However I’d like to have better understanding and control over my output listing. For starters there is an output node named nc_01 which looks like a no-connect to me. But as far as I can tell, everything seems connected. Can someone help me understand this output line, and maybe tracking down a possible no-connect?

Second, the output listing shows only collector and emitter node voltages for all of the transistors in my circuit. When I look at the spice netlist I see lots of .save statements including all the ones that correspond to the collectors and emitters, so I guess the simulation output is following the .save requests in the spice netlist. My questions are: 1) what determines which .save rows go into the spice netilist? 2) do I have any control over which .save lines go into the spice netlist? 3) what do I need to do to get the transistor base voltages added as .save statements in the spice netlist and to appear in the simulation output listing.

Also, I have a few nodes with a suffix “#branch” that I don’t understand. These nodes correspond with other nodes that I can easily identify. For example, I have a V_d node on my schematic, and that node appears in the simulator output. But the simulator output also has a node named “V_d#branch”. I’m not sure of why the “V_d#branch” node is there in the output.

Finally, while trying to get the transistor base voltages I tried using the probe button in the spice simulator. I click the button and then select the schematic but there is no indication that I am using the probe–instead I see the standard schematic cursor.

Thanks in advance for helping me.

skipt

2

Eeschema is primarily a tool to support PCB design. Output lines leading to nowhere at least deserve a warning. You may get rid of the non-connected issue by supplying a load, e.g. a 1G resistor (large enough to not disturb your circuit) to the output.

Typically all nodes with their voltage outputs are listed, although often with “strange” names. You may place labels to the nodes of interest to get the label as node name instead.

#branch data are currents. V_d#branch is the current through voltage source V_d.

You activate the probe button, go to the schematic, click onto your node(s) of interest and then go back to the simulator window to see these node names in the list of nodes to be plotted.

1 Like
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Thanks Holger, that is sinking in now.

My current efforts right now are aimed at analysis so I am spending more of my time with LTSpice. But when I get back into board design you will see more of me.

The final aha moment just came to me–working in LTSpice I noticed that polarized capacitors are not supported for the most part: DING DING DING capacitor polarization is obviously important to Kicad so that boards can be laid out but not so much to LTSpice. I did however find that some electrolytic suppliers are providing spice subckt models for their products so that more sophisticated analyses can model certain electrolytic frequency behaviors. For me all of that now drives home your point that Kicad is “primarily a tool to support PCB designs.”

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