When I make local net names for some connections in my schematic it doesn’t show up in the netlist while for others it does. Below is part of the project I’m working on. TEST2 shows up on the netlist, while TEST1 does not. In pcbnew, pin 39 becomes part of the 3.3VD net which is also my power plane. I would like to avoid that and just have pin 39 connect to C4. Is there any way to accomplish this without using global labels?
On another note as well, while researching this issue, I have found that everyone elses local net names are black while mine are yellow. Am I doing something wrong or is this simply part of an update?
Different labels have different priorities.
I think the highest priority are global labels then hierarchical labels and than local labels. But i could be wrong.
(The priority defines which name is chosen for the net.)
To your “problem”:
This is by design. If two different labels are connected via a wire, they become equivalent.
(In your case you connected the global label +3.3VD to test1)
See eeschem documentation:
Section 5.5.2. Connections (Wires and Labels) Note 4
In other words: Even if you switch out your local label against a global label, the pin 39 is still connected to your copper zone because you connected it with a wire to it.
(The only thing that would change is the net name. But i’m not even sure this changes. I don’t know how high the priority of the power labels is.)
Now the most important question:
What do you want to achieve. Why do you want this pin not to be connected to your 3v3 net? (And why do you connect it with a wire to this label if you don’t want it connected?)
I also see lack of use case for this problem.
However try putting “bypass” in schematic, smth like this with same local label on that pin. Not sure that this is going to work.
And regarding the color of local label go
Preferences > Set Colors Scheme
Well I have a noisy power supply and I need pin 39 to be able to grab something cleaner through the capacitors, but when I fill the power plane it fills in around the pin as well, circumventing the caps. Am I missing something fundamental here? Are those two cases the same?
Specify keepout area on the same layer like this blue rectangle. ( option underneath add filled areas on right toolbar ) In its settings tick only “no copper pour” and un-tick other options.
This has been my approach, but I have many of these sections and I was wondering if there was anyway to do it other wise, i.e. changing net names. Is there some way to only have the net fill pads and not traces? Or something I could have done differently in my schematic?
Those capacitors are virtually useless way out there!
There’s a crystal wedged right above there that I deleted temporarily to make my point, but duly noted I’ll move stuff around to get them closer. Thanks.