KiCad Spice Timestep Issues

I’m simulating a simple circuit in KiCad and ran into a problem with the time step variable. I had set it to 100k samples (1u / 100m) and ran a simulation. The simulation took forever and used about 10GB of RAM. This seemed a lot to me, so I increased the time step. But no matter the value, the simulation resolution is unchanged. I can even set the time step to 100m, which should result in a single sample, but I still get millions of samples.

Now I’m wondering if I’m doing something wrong or if this is a bug.


My guess is that the time step is no fixed value, but a max step size. And since the pulse “requires” a higher sample count, the final sample count is overwritten.

As far as I know, you cannot directly control the timestep. The tstep parameter is only a suggested initial starting time step, but the actual timestep is variable and will be reduced until one of the error estimation measures drops below a threshold. These latter measures are controlled through the .opt statement. I suggest starting with RELTOL, which you could probably reduce by a factor of 2-4. You are trading accuracy for simulation resource intensity. If that doesn’t help a lot, you could also increase VNTOL and ABSTOL by a factor of ten. By the way, it’s really easy to get into trouble messing with these parameters, but your circuit is very simple and well-behaved so it’s probably ok. Alway check the results to make sure they make sense.

This is a can of worms, by the way. For the general case, circuit simulation is difficult because most circuits are non-linear (sometimes highly) and time-varying. Your circuit is very simple, but the high-frequency behavior will force the timestep to be small in order to capture the behavior accurately. This, combined with the large final time value, forces a LOT of timesteps. It’s a fundamental problem in simulation.

Also, look up the simulation statements in the manual.

John

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Thanks! That is what I was looking for

Indeed the time step size here is determined by the pulse voltage train: rise and fall times 5n, width of the top 7.5n, period 25n. To hit the bottom and top edges of the pulse train during the simulation, the step size cannot be larger than 5n, width and period require 7.5n step size at top and bottom. Any larger step size would “smear out” the pulse train, with wrong results.

As John has said, you have to live with the two vastly differing time constants, the pulse train and the RC combination.

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